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Indirect branch instruction processing method and device

A branch instruction and processing method technology, which is applied in electrical digital data processing, program control design, instruments, etc., can solve the problems of excessive context switching and low translation efficiency, and achieve the effect of improving efficiency

Active Publication Date: 2012-09-12
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] The present invention provides an indirect branch instruction processing method and device to at least solve the problem of low translation efficiency caused by too many context switches in the binary translation process in the related art

Method used

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  • Indirect branch instruction processing method and device
  • Indirect branch instruction processing method and device
  • Indirect branch instruction processing method and device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] This embodiment provides a method for processing indirect branch instructions, such as figure 2 As shown, the method includes:

[0035] S202, load the cache array corresponding to the current basic block where the currently executed indirect branch instruction is located, wherein the record item in the cache array is used to record the target address of the executed indirect branch instruction in the current basic block; preferably, every A basic block corresponds to a cache array, and the entries in the cache array record the target addresses of the executed indirect branch instructions in the current basic block. Preferably, the process of recording the target address of the indirect branch instruction can be realized by recording the pointer of the structure corresponding to the basic block where the target address of the indirect branch instruction is located, wherein the above structure is used to store the corresponding basic block, but the present invention Not...

Embodiment 2

[0047] On the basis of the above-mentioned embodiment 1, this embodiment also provides an indirect branch instruction processing device, specifically, as image 3 As shown, the device includes: a loading unit 302, configured to load a cache array corresponding to the current basic block where the currently executed indirect branch instruction is located, wherein the record items in the cache array are used to record the executed in the current basic block. The target address of the indirect branch instruction; preferably, each basic block corresponds to a cache array, and the records in the cache array record the target address of the indirect branch instruction that has been executed in the current basic block. Preferably, the indirect branch instruction can be recorded by recording the The process of recording the target address of the indirect branch instruction is realized by the pointer of the structure body corresponding to the basic block where the target address of the ...

Embodiment 3

[0058] On the basis of the above-mentioned embodiment 1 and embodiment 2, the present invention also provides a specific indirect branch instruction processing scheme applied to binary translation, which comprises:

[0059] Step 1, add a cache array for each basic block, and this cache array is used to cache the target address of the indirect branch instruction. Preferably, the process of recording the target address of the indirect branch instruction can be realized by recording the pointer of the structure corresponding to the basic block where the target address of the indirect branch instruction is located, wherein the above structure is used to store the corresponding basic block, but the present invention Not limited to this, other alternative ways can also be used to record the target address of the indirect branch instruction.

[0060] Step 2, when the indirect branch instruction is executed for the first time, because the cache array of the basic block where the indir...

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Abstract

The invention discloses an indirect branch instruction processing method and an indirect branch instruction processing device, wherein the method comprises the steps: loading caching array corresponding to a current basic block in which an indirect branch instruction currently executing is, wherein a record item in the caching array is used for recording a target address of the executed indirect branch instruction in the current basic block; judging whether the target address of the indirect branch instruction currently executing is identical with the recorded target address of the corresponding record item in the caching array, if yes, skipping to the target address of the indirect branch instruction currently executing, and starting executing codes from the target address of the indirect branch instruction currently executing. According to the method, the problem that context switches are excessive in binary translation process to cause low translation efficiency can be solved, and the effect of improving the efficiency of a binary translation system is achieved.

Description

technical field [0001] The invention relates to the field of dynamic binary translation, in particular to an indirect branch instruction processing method and device. Background technique [0002] Binary translation technology refers to the conversion of binary code executed on one architecture into binary code that can be executed by another architecture. In dynamic binary translation technology, performance is the most concerned topic. Many research works have shown that the handling of indirect instructions is a key factor affecting performance. In the source program code sequence, a series of code segments marked by jump instructions are called basic blocks, and dynamic binary translation takes basic blocks (or code blocks) as the basic translation and execution unit, and the average application program every 4- 7 instructions have a jump instruction. There are two types of jump instructions: deterministic jumps and non-deterministic jumps. Deterministic jumps includ...

Claims

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Application Information

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IPC IPC(8): G06F9/34G06F9/45
CPCG06F9/30061
Inventor 廖银靳国杰高翔
Owner LOONGSON TECH CORP
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