Method and system for branch target prediction using path information

Abstract

A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed by the addition of one or more bits to the register. The cache is indexed by performing an operation on a portion of the current instruction address and the path register; the entry returned, if any, may be used to predict the target of the current instruction.

Description

BACKGROUND OF THE INVENTION [0001] I. Field of the Invention [0002] The present invention relates to the field of computer systems. More specifically, the present invention relates to microprocessors, in particular to the prediction of branch instructions. [0003] II. Background Information [0004] Microprocessors (or “processors”) execute a series of program instructions, each instruction having an address. Typically instructions are executed in sequence, with branch instructions causing out of sequence execution by causing the processor to branch to an instruction. Pipelined processors generally process instructions in a sequence of stages, such as fetch, decode, execute, and retire, forming a pipeline. Different aspects of different instructions are processed at the same time by different stages forming the pipeline. While one instruction is being fetched from memory, another is being decoded, another is being executed, etc. [0005] When it is known whether or not an instruction bei...

AI Technical Summary

Benefits of technology

[0014] A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed by the addition of one or more bits to the register. The cache is indexed by performing an operation on a portion of the current instruction address and the path register; the entry returned, if any, may be used to predict the target of the current instruction.

Problems solved by technology

Thus, a certain amount of processing effort, taking a certain amount of time, is wasted.

The delay in fetching the next instruction will cause each stage of the pipeline to be idle for a period of time.

If the prediction is incorrect a stall will occur; thus branch prediction mechanisms are only worthwhile if they predict target addresses with some amount of accuracy.

Branch prediction mechanisms are costly in terms of processor resources.

A tradeoff occurs between devoting resources to branch prediction mechanisms and their accuracy.

It is costly to implement branch prediction mechanisms.

However, the less resources devoted to such mechanisms the less accurate they are.

Branch prediction accuracy suffers when less information is stored as branch history, less information is used to index prediction tables and less information is stored in prediction tables.

Furthermore, branch prediction methods which are accurate and efficient for and appropriate for conditional branches may not be accurate and efficient for and appropriate for indirect branches.

Images