Instruction set optimization

Abstract

The invention provides an instruction set optimization method. In one aspect, the invention provides a microprocessor, which comprises: an instruction memory for mixed storage of first-length instructions and second-length instructions with different lengths, the first-length instructions are shorter than the second-length instructions and the two are distinguished by adopting operational codes; an instruction extraction unit, which extracts the instructions in mixed storage from the instruction memory and separates the first-length instructions from the second-length instructions according to the operational codes; an instruction decoding unit, which decodes the first-length instructions and the second-length instructions respectively; and a jump operation unit, which, in jump operation, transfers instructions to the boundary of either the first-length or the second-length instructions. By adopting the optimized instruction set, the program code size can be significantly reduced.

Description

technical field [0001] The present invention relates to microprocessors, and in particular to the optimization of instruction sets used by microprocessors. Background technique [0002] Today, memory subsystems are increasingly costlier than microprocessors. Compressing code to fit memory subsystems constrained by cost or space has become an important business in embedded system development. To save storage costs, on the one hand, it is necessary to write compact codes; on the other hand, the instruction set of the microprocessor also has a great impact on memory consumption. Usually, the instruction of the microprocessor is 32 bits, and some instructions use up to 32 bits, such as ADD Rd, Ra, Rb. Some instructions do not require 32 bits, such as JUMP and PUSH instructions. To this end, someone designed a 16-bit instruction subset or length instruction to reduce the code size. [0003] Take ARM's code compression scheme (Thumb) as an example. Thumb is actually an indepe...

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