Instruction set optimization

A technology of instruction and instruction memory, which is applied in the field of instruction set optimization and can solve the problem of waste of storage space

Inactive Publication Date: 2009-01-14
苏州简约纳电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It can be seen from Figure 2(b) that there is a certain waste of storage space

Method used

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  • Instruction set optimization
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Examples

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Embodiment Construction

[0019] image 3 is a diagram of the instruction format according to one embodiment of the present invention. Such as image 3 As shown, there is a 32-bit storage space. The 32-bit storage space may store one 32-bit instruction, or two 16-bit instructions. When decoding, first treat the 32-bit word as a 32-bit instruction, and check bits 27-31. If bits 27-31 are not the opcode of a 16-bit instruction, it indicates a 32-bit instruction. If there is an opcode for a 16-bit instruction at bits 27-31, it indicates that the upper 16 bits (bits 16-31) of the 32-bit word belong to a 16-bit instruction. Obviously, the lower 16 bits (bits 0-15) of a 32-bit word also belong to a 16-bit instruction, so the lower 16 bits are decoded into another 16-bit instruction.

[0020] It should be noted that the operation code is not only set in the upper 5 bits of 16 bits. It can be set at any position of 16 bits, and can also be composed of a certain number of bits.

[0021] According to the ...

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Abstract

The invention provides an instruction set optimization method. In one aspect, the invention provides a microprocessor, which comprises: an instruction memory for mixed storage of first-length instructions and second-length instructions with different lengths, the first-length instructions are shorter than the second-length instructions and the two are distinguished by adopting operational codes; an instruction extraction unit, which extracts the instructions in mixed storage from the instruction memory and separates the first-length instructions from the second-length instructions according to the operational codes; an instruction decoding unit, which decodes the first-length instructions and the second-length instructions respectively; and a jump operation unit, which, in jump operation, transfers instructions to the boundary of either the first-length or the second-length instructions. By adopting the optimized instruction set, the program code size can be significantly reduced.

Description

technical field [0001] The present invention relates to microprocessors, and in particular to the optimization of instruction sets used by microprocessors. Background technique [0002] Today, memory subsystems are increasingly costlier than microprocessors. Compressing code to fit memory subsystems constrained by cost or space has become an important business in embedded system development. To save storage costs, on the one hand, it is necessary to write compact codes; on the other hand, the instruction set of the microprocessor also has a great impact on memory consumption. Usually, the instruction of the microprocessor is 32 bits, and some instructions use up to 32 bits, such as ADD Rd, Ra, Rb. Some instructions do not require 32 bits, such as JUMP and PUSH instructions. To this end, someone designed a 16-bit instruction subset or length instruction to reduce the code size. [0003] Take ARM's code compression scheme (Thumb) as an example. Thumb is actually an indepe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30
Inventor 陈新中卢佳文梅思行
Owner 苏州简约纳电子有限公司
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