The invention discloses a method for verifying large-scale interconnection chips based on a BFM, and belongs to the field of chip design. The method comprises the steps that operation of sending a bus protocol command is achieved through utilizing routers and physical layer accesses of the chips between BFM simulation nodes; the BFM is connected with the chips of the same node through pli interfaces, the BFM simulates socket models between the nodes, and BFM logic verification environment is established; a system C simulates a CPU to send a drive signal to the logic verification environment at the BFM end, the socket models send verification data to chips through the pli interfaces, after the chips respond, chip feedback data are recorded, and error detection records are achieved through the system C. By means of the method for verifying the large-scale interconnection chips based on the BFM, the complexity degree of verification is reduced, the comprehensive validation is guaranteed, the universality of verification drive is improved, and by means of the advantage of taking the system C as a software language, the operation and the data monitoring with higher abstraction degree are achieved.