10 results about "Software language" patented technology

The invention relates to the technical field of PLC programming language testing in the field of industrial automation control, in particular to an IEC 61131-3-based PLC programming software language function full coverage testing method, which comprises the following steps: establishing a structured test table based on functions of five PLC programming languages; based on the content of the structured test table, a plurality of different function points to be tested are determined, and a test program complete set is determined based on the function points to be tested; the test program complete set is iteratively updated according to a test standard; importing the test program complete set into to-be-tested PLC programming software, and testing grammar analysis, compiling results and runtime behaviors to obtain test data; generating a technical list based on the test data; according to the invention, the test comprehensiveness of the PLC programming language can be improved.

The invention relates to the technical field of computers, and provides a synchronous task execution method and device, equipment and a medium, and the method comprises the steps: receiving a task queue set submitted by a plurality of user processes; obtaining a first execution task from a first task queue in the task queue set; under the condition that the first execution task is a synchronization task, simulating the first execution task based on a software language, and realizing a synchronization mechanism corresponding to the first execution task; and based on the synchronization mechanism and the scheduling rule, executing the execution task in the task queue set. The tasks in the task queues are scheduled through the synchronization mechanism corresponding to the software simulation synchronization task, so that the tasks are sequentially executed according to the expected sequence of the user process, the software executes the synchronization task, meanwhile, the task queues which do not meet the execution condition are switched in real time according to the scheduling rule in software simulation, and the execution efficiency is improved. And continuous waiting is avoided, and deadlock between the processes is further avoided when the multiple processes use the equipment at the same time.

The present application relates to the technical field of computer, and provides a synchronous task execution method, device, equipment and medium, the method comprises the following steps: receiving a task queue set submitted by multiple user processes; obtaining a first execution task from a first task queue in the task queue set; in the case that the first execution task is a synchronous task, simulating the first execution task based on a software language, realizing a synchronization mechanism corresponding to the first execution task; based on the synchronization mechanism and a scheduling rule, executing the execution tasks in the task queue set. The present application simulates the synchronization mechanism corresponding to the synchronous task by software to schedule the tasks in each task queue, so that each task is executed in turn according to the expected order of the user process, realizing the software to execute the synchronous task, and at the same time, the task queue that does not meet the execution condition is switched in real time according to the scheduling rule in the software simulation, avoiding waiting all the time, and further avoiding the deadlock between processes when multiple processes use the device simultaneously.

Embodiments of the present disclosure provide an operator testing method and device, equipment, readable storage medium and program product, which are related to the field of software testing, and the application scenarios include but are not limited to the operator testing scenario. The method comprises: obtaining an original neural network operator and a target software language description, the original neural network operator comprising a target function, and the target software language description being obtained by language conversion of a hardware primitive in the target function in a target software language; determining a decorator of the target function, the decorator of the target function comprising a target object of a preset target class, the target object of the target class being obtained by encapsulating the target function through the target class; updating the original neural network operator based on the target software language description, the decorator of the target function and the target class to obtain an updated neural network operator; and testing the updated neural network operator in a test mode of the target software language to obtain a test result corresponding to the updated neural network operator.

The present application provides a method, apparatus, electronic device and computer-readable storage medium for calling a chip verification platform. By compiling and running a software language calling program, there are software method interfaces encapsulated in various software languages in a preset compatible link library. A matching software method interface is determined for a calling function to be executed in the software language calling program. Then, by determining the matching software method interface with the calling function, the corresponding verification link file is called for execution, and the execution result is output as the return value of the calling function. Through the software language calling program, the execution result of the verification link file after the encapsulation of the functional method of the chip verification platform is obtained. The call is changed from being made through a hardware description language to being made through a software language calling program, reducing the learning cost of the hardware description language with high learning complexity and lowering the difficulty of chip verification learning.

This invention belongs to the field of software porting technology, and specifically relates to a software intelligent porting assistance method and system based on the SW processor. It includes: constructing a SW processor-specific feature knowledge base; performing static analysis on the code of the software to be ported and storing it in a vector database to construct a knowledge base vector index, thereby comparing code differences; performing code preprocessing based on the analysis and vector index results, as well as the SW architecture rules and x86 to SW architecture conversion rules in the specific feature knowledge base; identifying the software language and system environment of the software to be ported and compiling it, generating compilation error logs if compilation errors occur; retrieving errors from the compilation logs, and using the SW large model to identify and call repair tools for code modification via function call functionality; this invention solves the problems of poor compatibility, low efficiency, and poor stability of existing tools adapted to this processor.

In some embodiments, a method receives a schema registry in a file. The schema registry aggregates schema files for a data model that is associated with a database system used by servers and consumer devices. The schema files is in a first software language that describes objects in the data model, and the schema registry is in a second software language used by the consumer devices. A first function in the schema registry is executed for an object to retrieve an original schema for the object in the schema files to create first software code for the object with the original schema for an application that uses the data model. A second function in the schema registry is executed for the object to generate a new object from the original schema for the object to create second software code for a new object with the original schema for the application.

The application relates to the chip technical field, in particular to a verification system based on a software storage model, which comprises a driving module, a first conversion interface, an RTL module, a second conversion interface and a storage model; the driving module and the storage model are realized based on a software language; the first conversion interface and the second conversion interface are realized based on the software language and a hardware language; the RTL module is realized based on the hardware language; the RTL module is used for storing RTL codes of a chip design to be tested; the driving module is connected with the first conversion interface; the first conversion interface is connected with the RTL module; the RTL module is connected with the second conversion interface; the storage model comprises a front door access path and a back door access path; the RTL module is connected with the storage model through the front door access path; and the driving module is connected with the storage model through the back door access path. The application reduces chip verification cost, improves chip verification efficiency and verification system performance.

In some embodiments, a method receives a schema registry in a file. The schema registry aggregates schema files for a data model that is associated with a database system used by servers and consumer devices. The schema files is in a first software language that describes objects in the data model, and the schema registry is in a second software language used by the consumer devices. A first function in the schema registry is executed for an object to retrieve an original schema for the object in the schema files to create first software code for the object with the original schema for an application that uses the data model. A second function in the schema registry is executed for the object to generate a new object from the original schema for the object to create second software code for a new object with the original schema for the application.

The application provides a device, method, equipment and storage medium based on software and hardware joint verification, the device comprises: a verification platform, the verification platform is provided with an interface, the verification platform is electrically connected with an NPU to be verified based on the interface; the verification platform is used for obtaining configuration information; the configuration information is transmitted to the NPU through the interface; the configuration information is obtained based on a software language; the configuration information comprises clock parameters, interrupt parameters, mode parameters and processing parameters; the verification platform is also used for obtaining a verification result based on the interface; the verification result indicates whether the NPU is normal, the verification result is obtained by analyzing a running result of the software language, the running result is obtained by the NPU based on an interrupt source and a processing result, and the processing result is obtained by the NPU based on the clock, the working mode and the processing data mode, and processing verification data. The technical scheme of the application can improve the operator verification efficiency of the NPU.