Method for quickly obtaining node simulation state in digital gate level circuit

Abstract

The invention discloses a method for quickly obtaining a node simulation state in a digital gate level circuit, and mainly solves the problems of high difficulty and long time consumption on the aspect of gate level netlist simulation verification in the prior art. The method comprises the following steps that: 1) according to a given gate level circuit, obtaining a connection relationship between the external input and the external output of the gate level circuit and an internal node; 2) describing the logic relationship of the gate level circuit with a hardware language to generate a gate level circuit logic description file; 3) according to the connection relationship in 1), converting the gate level circuit into an RTL (Register-Transfer Level) description unit; 4) according to the connection relationship of the gate level circuit, generating a simulation test file with a software language; and 5) adding the files generated from S2) to S4) into commercial simulation software to be simulated to obtain the simulation state of the internal node of the gate level circuit. By use of the method, simulation complexity and time can be greatly reduced, gate level netlist simulation verification is improved, and the method can be used for extracting gate level netlist key nodes and accelerating the gate level netlist simulation verification.

Description

technical field [0001] The invention belongs to the technical field of circuit processing, and in particular relates to a method for quickly acquiring the simulation state of internal nodes of a digital gate-level circuit, which can be used in the tracking signal extraction stage in post-silicon verification based on simulation. Background technique [0002] As is well known in the industry, the design of integrated circuit chips is roughly divided into two parts: front-end logic design synthesis and back-end physical design synthesis. The front-end logic design includes basic RTL programming and simulation, logic synthesis, static timing analysis STA and formal verification and other steps; the back-end physical design includes clock tree synthesis, layout and routing, power analysis, physical verification and design for manufacturability Wait for multiple steps. In chip design, the definition, development, synthesis, integration, and verification of front-end logic are im...

AI Technical Summary

Problems solved by technology

When using traditional simulation tools for simulation verification, it is necessary to write test code files for each reference circuit separately, which is very inconvenient for large gate-level circuits

Although the existing gate-level netlist simulator solves this problem very well, with the development of SoC design techniques and more and more diverse application requirements, the SoC architecture is becoming more and more complex, and the chip scale is becoming more and more complex. Huge, the simulation difficulty of existing simulators is getting more and more difficult, and the time consumed is getting longer and longer, which seriously hinders the progress of verification work

Images