Method for measuring static quality of FPGA software

A static quality and software quality technology, applied in software testing/debugging, instrumentation, electrical digital data processing, etc., can solve problems such as unfairness and over-roughness, improve efficiency, reduce test costs, and quantify static testing quality effect

Inactive Publication Date: 2017-11-10
10TH RES INST OF CETC
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Problems solved by technology

Secondly, the usual practice of FPGA software testing quality is to use sof

Method used

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  • Method for measuring static quality of FPGA software
  • Method for measuring static quality of FPGA software
  • Method for measuring static quality of FPGA software

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Embodiment Construction

[0025] refer to figure 1 . In order to be able to objectively evaluate the quality of inspection results, the evaluation process needs to be divided into "three steps".

[0026] next figure 1 In the entire evaluation process shown, step-by-step includes three processes of analysis, calculation and evaluation. In the evaluation process, more attention is paid to the analysis and calculation of metric elements. Different from the traditional evaluation process of FPGA software quality measurement, the new process will Transform and give the final evaluation results.

[0027] Step 1, analyze metrics: in the FPGA software including VHDL and Verilog, analyze and evaluate the types of metrics violated, filter out the metrics that reflect the value of software quality, and set the metrics and their weighting coefficients , classify and weight FPGA software metrics, and assign larger values ​​to those that have a great impact on software code quality and are significantly different...

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Abstract

A method for measuring the static quality of FPGA software disclosed by the present invention aims to provide a method that can effectively reduce the number of verification tests and quantify the static test quality of software codes. The present invention is realized through the following technical solutions, including VHDL and Verilog In the FPGA software in different languages, the metric elements that reflect the value of software quality are screened out, and the FPGA software metric elements are classified and weighted; the evaluation rule sets that reflect a wide coverage and high degree of influence are selected, and the relevant weighting coefficients of the metric elements are extracted. Determine the severity of the impact, determine the number of evaluation metrics, and establish the analysis metrics and FPGA software quality evaluation model and rule set classification appendix table; according to the fault statistics of the reference standard GJB 2423A, calculate the total number of metrics A and the metrics and The specified metric element score is used to calculate the total number of metric element defects and the evaluation rules to give the metric evaluation result.

Description

technical field [0001] The invention relates to a method for measuring the static quality of programmable logic device (FPGA) software, which includes the classification of measurement elements, the design of weight coefficients of measurement elements, a measurement calculation method, an evaluation rule and an evaluation flow. Background technique [0002] At present, the mainstream trend of information security equipment and special chip design is to express the design intent in HDL (Hardware Description Language), FPGA as the hardware carrier, computer as the design and development tool, and EDA software as the development environment. In order to improve the design quality of information security equipment, each link of its research and design must be reviewed. FPGA has the characteristics of high integration, low power consumption, flexible use and short development cycle, etc., and is widely used in the field of digital system design. FPGA software testing has receiv...

Claims

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Application Information

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IPC IPC(8): G06F11/36
CPCG06F11/362
Inventor 李晨阳孙肖陈晟飞王静
Owner 10TH RES INST OF CETC
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