Patents
Literature
Patsnap Eureka AI that helps you search prior art, draft patents, and assess FTO risks, powered by patent and scientific literature data.

4 results about "Write barrier" patented technology

In operating systems, write barrier is a mechanism for enforcing a particular ordering in a sequence of writes to a storage system in a computer system. For example, a write barrier in a file system is a mechanism (program logic) that ensures that in-memory file system state is written out to persistent storage in the correct order.

Concurrent lazy reference counting in an old garbage collection generation

Techniques for concurrent lazy reference tracking in an old garbage collection generation are disclosed, including: encountering, by a mutator thread during a garbage collection epoch, a first instruction to write a first value to a field; responsive to encountering the first instruction to write the first value to the field: entering a slow-path write barrier; performing, by the slow-path write barrier, a first one or more reference counting operations with respect to the field; encountering, by the mutator thread during the first garbage collection epoch and subsequent to encountering the first instruction to write the first value to the field, a second instruction to write a second value to the field; responsive to encountering the second instruction to write the second value to the field: entering a fast-path write barrier; wherein the fast-path write barrier does not perform any reference counting operations with respect to the field.
Owner:ORACLE INT CORP

Memory-Governed Supervisory and Evolutionary System with Adjudicated Memory Admission, Write-Barrier Constitutional Constraints, and Execution Separation Architecture

A memory-governed supervisory and evolutionary system is disclosed in which authority to influence system evolution is constitutionally constrained through adjudicated memory admission. Information from external sources and internally generated outputs is recorded as candidate memory resources within a structured memory architecture and rendered ineffective prior to adjudication by a write barrier. Admission occurs under a governance framework defining admissible evolution ranges, and system evolution arises exclusively from admitted structured memory resources. Supervisory outputs generated from admitted memory resources are expressive and non-executable, while execution and enforcement actions occur exclusively outside the system boundary. The disclosed architecture structurally separates information, authority, and execution, preventing delegation of authority to computation, intelligence, or external execution and enabling governed system evolution across asynchronous and heterogeneous environments.
Owner:LED SMART

A data transmission method for digital phased array

The application discloses a data transmission method of a digital phased array, and particularly relates to the field of communication transmission, and is used for solving the problem of inconsistent configuration change effective boundary of multiple receiving ends under link disorder; a sending end encapsulates sampling data into a data frame with a write frame serial number and frame integrity check information and sends the data frame according to the frame serial number, and inserts a barrier frame with a write barrier serial number before configuration change; a receiving end records a barrier landing frame serial number, a continuous tail frame serial number and generates a neighborhood frame serial number event string after entering a barrier frozen state, and sends a barrier reply; a sending end forms a submission judgment according to the barrier reply, determines a unified submission frame serial number, and sends a submission frame with a write configuration version number and the unified submission frame serial number; and the receiving end writes a new configuration into a submission area, loads the new configuration when the data frame serial number reaches the unified submission frame serial number, and returns a submission reply.
Owner:SHAANXI SHENGSHI QIANYUAN TECHNOLOGY CO LTD

Data transmission method of digital phased array

The invention discloses a data transmission method of a digital phased array, particularly relates to the field of communication transmission, and is used for solving the problem that configuration change effective boundaries of multiple receiving ends are inconsistent under the condition of out-of-order links. Sampled data is packaged into a data frame written with a frame sequence number and frame integrity verification information through a sending end, the data frame is sent according to the frame sequence number, and a barrier frame written with a barrier sequence number is inserted before configuration change; after entering a barrier freezing state, a receiving end records a barrier drop point frame sequence number and a continuous tail frame sequence number, generates a neighborhood frame sequence event string and sends a barrier receipt; the sending end forms submission judgment according to the barrier receipt, determines a uniform submission frame sequence number and then sends a submission frame written with the configuration version number and the uniform submission frame sequence number; and the receiving end writes the new configuration into the to-be-submitted area, loads and takes effect when the frame number of the data frame reaches the uniform submission frame number, and returns a submission receipt.
Owner:SHAANXI SHENGSHI QIANYUAN TECHNOLOGY CO LTD