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Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

A technology of computers and microprocessors, which is applied in the direction of machine execution devices, calculations, concurrent instruction execution, etc., to achieve the effect of saving operation code space

Inactive Publication Date: 2006-10-11
MIPS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Another problem that exists in multithreaded processors is that the scheduling policy keeps a thread running until it is blocked by some other resource, and a thread that is not blocked by any resource still relinquishes the processor to other threads

Method used

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  • Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
  • Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
  • Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

Examples

Experimental program
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Effect test

no. 1 example

[0102] The YIELD instruction causes the current thread to be selectively descheduled. In a first embodiment, the format of a YIELD instruction 600 is as Figure 6 shown, while Figure 32 Flowchart 3200 in describes system operation according to one embodiment of the invention, using Figure 6 The function of the YIELD instruction. A second embodiment of the YIELD instruction 3500 is referred to below Figure 35 to Figure 40 to describe.

[0103] For example, YIELD instruction 600 takes a single operand value in the GPR identified in field 602(rs). In one embodiment a GPR is used, but in alternative embodiments its operand values ​​may be stored or retrieved from virtually any system-accessible data storage device (eg, non-GPR registers, memory, etc.). In an embodiment, the content of GPR rs may be considered a descriptor of the circumstances under which the issuing thread should be rescheduled. If the content of the GPR rs is zero (that is, the value of the operand is ze...

no. 2 example

[0262] refer to Figure 35 , a block diagram showing the format of the YIELD instruction 3500 in another embodiment of the present invention. Figure 35 The YIELD instruction 3500 is similar to Figure 6 instruction 600; however, Figure 35 The YIELD instruction 3500 has two differences. First, the meaning of the value stored in the register specified by the rs field 3502 is somewhat different, as described below. second, Figure 35 The YIELD instruction 3500 also includes a second operand field rd 3504 . exist Figure 35 In an embodiment of , the rd operand field 3504 contains bits 11 through 15 of the YIELD instruction 3500 . The rd operand field 3504 specifies a destination register (eg, 6PR) that receives a result value upon completion of the YIELD instruction 3500, as described below.

[0263] refer to Figure 36 , showing the invention Figure 35 In another embodiment, a block diagram of a processor core 3302 executing the YIELD instruction 3500. Figure 36 A p...

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Abstract

A yield instruction for execution in a multithreaded microprocessor is disclosed. The yield instruction includes an operand. If the operand is zero the microprocessor terminates the program thread including the yield instruction. If the operand is -1 the microprocessor unconditionally reschedules the program thread. If the operand is a positive integer the microprocessor views the operand as a bit vector specifying one or more yield qualifier inputs, such as interrupt signals, and conditionally reschedules the thread based on the qualifier inputs and bit vector values. The microprocessor also includes a mask register that specifies a bit vector of the qualifier inputs. If the operand specifies a qualifier input not also specified in the mask register, an exception to the instruction is raised. The instruction returns a value specifying the values of the qualifier inputs qualified by the mask register value.

Description

[0001] [Cross-references to related patent applications] [0002] This patent application is a continuation-in-part (CIP) of the following commonly-owned, non-provisional U.S. Patent Applications, which are hereby incorporated by reference: [0003] U.S. Patent Application No. 10 / 684,350 (MIPS.0188-01-US), filed October 10, 2003, and entitled "Mechanisms for Ensuring Quality of Service for Program Execution on a Multithreaded Processor"; and [0004] US Patent Application No. 10 / 684,348 (MIPS.0189-00-US), filed October 10, 2003, is entitled "Integrated Mechanism for Suspending and Deallocating Computational Threads in a Processor." [0005] The above-mentioned commonly-owned non-provisional U.S. patent application is claiming the following U.S. provisional patent application, which are hereby incorporated by reference: [0006] U.S. Provisional Patent Application No. 60 / 499,180 (MIPS.0188-00-US), filed August 28, 2003, entitled "Special Extensions for Multithreaded Applications...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F9/30G06F9/46G06F9/318
Inventor 凯文·基塞尔
Owner MIPS TECH INC
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