High-speed audio and video data encryption system and method based on FPGA

Abstract

The invention discloses a system and a method for encrypting high-speed audio and video data based on an FPGA (Field Programmable Gate Array). The system mainly comprises an optical module interface, an FPGA module, a DDR4 (Double Data Rate 4), a FLASH and an HDMI (High Definition Multimedia Interface) TX interface. Wherein the FPGA module internally comprises a self-designed custom protocol processing module, a cache control module, a key management module and a data encryption module; the optical module interface is used for receiving audio and video data in a user-defined format; the user-defined protocol processing module analyzes effective audio and video data according to a user-defined message format, and the data is cached in a DDR4 (Double Data Rate 4) by a cache module; the key management module generates a key used for data encryption through an SM2 algorithm; the data encryption module realizes hardware encryption through the SM4 algorithm module; and the HDMI output interface module converts the encrypted audio and video data into an HDMI format and outputs the converted audio and video data at an HDMI TX interface. According to the high-speed data encryption method based on FPGA hardware logic, an optical module interface and an HDMI interface are combined, and an efficient and safe audio and video data encryption solution is provided.

Description

Technical Field

[0001] The present invention relates to the technical field of audio and video encryption, and in particular to a system and method for high-speed audio and video data encryption based on FPGA. Background Art

[0002] Audio and video data encryption technology involves encrypting audio and video content to ensure data security and prevent unauthorized access and leakage. Audio and video encryption technology has become an important means to ensure data security, privacy protection, and copyright protection.

[0003] With the popularization of Internet applications and the increasing demand for audio and video data transmission, audio and video data encryption technology is also constantly improving, and a faster encryption process is needed for large amounts of data. The advantages of hardware encryption algorithms mainly lie in providing higher security, stronger performance, lower system resource consumption, and higher anti-tampering capabilities. It can provide more efficient and secure solutions than software encryption in application scenarios such as large-scale data encryption, key management, and digital signatures.

[0004] The present invention provides an efficient and secure video data encryption solution based on FPGA high-speed data encryption technology, combined with optical module interface and HDMI interface. The system can realize real-time encryption in high-speed data transmission, support secure key management, and is widely used in digital video protection, industrial control, telemedicine and other fields. With its high performance, low latency and strong security, the system can effectively solve the privacy protection and data security problems in the process of large data transmission. Summary of the invention

[0005] The purpose of the present invention is to provide a system and method for high-speed audio and video data encryption based on FPGA, so as to solve the problems of large delay and low security in the existing audio and video data encryption process.

[0006] In order to achieve the above-mentioned purpose, the present invention designs a system and method for high-speed audio and video data encryption based on FPGA, including an optical module interface, an FPGA module, DDR4, FLASH and HDMI TX interface; the FPGA module internally contains a custom protocol processing module, a cache control module, a key management module and a data encryption module.

[0007] Preferably, the FPGA module uses the XCVU13P chip of the VIRTEX ULTRASCALE+ series as the main control chip for audio and video data encryption. The chip integrates multiple sets of GTY high-speed interfaces, and each channel supports a data transmission rate of 32.75Gbps.

[0008] The optical module interface receives audio and video data in a user-defined format, and the specific audio and video transmission format is flexibly determined by the application scenario and the protocol standard used.

[0009] Preferably, the optical module interface adopts a QSFP28 interface, which is physically compatible with QSFP+ and QSFP interfaces. The main feature is that it provides 4 independent data channels, can support a rate of 28Gbps per channel, can achieve a total bandwidth of up to 100Gbps, and ensures efficient transmission of audio and video data. The modular design allows users to flexibly choose different types of modules according to their needs, such as optical modules that support different transmission distances (short distance, medium distance and long distance). By replacing the module, it can adapt to different needs.

[0010] Preferably, the audio and video data input by the optical module interface is encoded in Aurora 64B66B format, which is applied to newer standards such as QSFP28 and above. 64-bit data is transmitted via 66 bits, which is more efficient than 8b / 10b encoding, can reduce overhead and increase data transmission rate.

[0011] The DDR4 caches audio and video data in a custom format.

[0012] Preferably, the DDR4 adopts a SO-DIMM interface, and a DDR4 memory stick supporting the interface can be used directly, which greatly simplifies the design and facilitates subsequent cache upgrades, and supports a maximum of 64GB of memory sticks.

[0013] The custom protocol processing module receives the audio and video data uploaded by the optical module interface of the four channels, first performs serial-to-parallel conversion, uniformly converts it into data with a bit width of 32 bits, and then parses out valid audio and video data and data ID according to the custom message format. The audio and video data bit width is 128 bits, and the data ID bit width is 8 bits. The valid audio and video data and data ID are sent to the cache control module.

[0014] The custom protocol processing module generates a message according to the custom protocol, including 4 serial input channels, namely data_in0, data_in1, data_in2, data_in4, input clock clk_in, data valid signal valid, output clock clk_out, data interface data_out[127:0] and data ID interface id_out[7:0]. When the valid signal is high, the data is valid, and the custom protocol processing module outputs 128-bit data at the data interface data_out[127:0] and 8-bit data ID at the data ID interface id_out[7:0] synchronously with the clk_out clock signal.

[0015] The cache control module caches the audio and video data uploaded by the custom protocol processing module to DDR4 through the AXI bus, and sends the audio and video data to be processed in DDR4 to the data encryption module;

[0016] The key management module generates a key for data encryption through the SM2 algorithm and sends the key to the cache register of the data encryption module;

[0017] The data encryption module performs hardware encryption processing on the audio and video data to be processed by the SM4 algorithm module to obtain the encrypted data ciphertext.

[0018] The HDMI output interface module converts the encrypted audio and video data into HDMI format according to the HDMI 2.0 protocol and outputs it at the HDMI TX interface.

[0019] Compared with the prior art, the beneficial effects of the present invention are: a system and method for high-speed audio and video data encryption based on FPGA. The optical module interface is used as the audio and video data input interface, which has the characteristics of ultra-high bandwidth, low latency, strong anti-interference ability, low power consumption and high security, and is particularly suitable for large-scale, high-quality audio and video transmission scenarios; the SM4 encryption algorithm is implemented using FPGA hardware logic to achieve real-time encryption in high-speed data transmission; combined with the optical module interface input and HDMI interface output, an efficient and secure audio and video data encryption solution is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a functional block diagram of a high-speed audio and video data encryption system based on FPGA of the present invention;

[0021] Figure 2 It is a schematic diagram of the interface of the custom protocol processing module of the present invention;

[0022] Figure 3 It is a flow chart of the cooperative work of various sub-modules inside the FPGA module of the present invention. DETAILED DESCRIPTION

[0023] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments, but the embodiments of the present invention are not limited thereto.

[0024] like Figure 1 As shown, the present invention proposes a system and method for high-speed audio and video data encryption based on FPGA, including an optical module interface, an FPGA module, DDR4, FLASH and HDMI TX interface; the FPGA module internally includes a custom protocol processing module, a cache control module, a key management module and a data encryption module;

[0025] Specifically, the FPGA module uses the XCVU13P chip of the VIRTEX ULTRASCALE+ series as the main control chip for audio and video data encryption. The chip integrates multiple sets of GTY high-speed interfaces, each channel supports a data transmission rate of 32.75Gbps, and uses 4 sets of GTY interfaces of the same BANK to connect to the 4 data channels of the optical module interface, which can achieve a total bandwidth of more than 100Gbps.

[0026] The optical module interface receives audio and video data in a user-defined format.

[0027] Specifically, the optical module interface adopts a QSFP28 interface, and by accessing the QSFP28 module, the QSFP28 module provides a high-speed signal transmission channel, supporting a variety of different data formats and protocols. The specific audio and video transmission format is determined by the specific application scenario and the protocol standard used. The input audio and video data is encoded in Aurora 64B66B format, which is applied to newer standards such as QSFP28 and above. 64-bit data is transmitted via 66 bits, which is more efficient than 8b / 10b encoding, can reduce overhead, and increase data transmission rate.

[0028] The DDR4 caches audio and video data in a custom format.

[0029] Specifically, the SO-DIMM interface used by the DDR4 is designed with data integrity and reliability in mind, and is equipped with a version with ECC (Error Correcting Code) function for correcting single-bit errors in memory, making it suitable for applications that require high reliability.

[0030] The custom protocol processing module receives the audio and video data uploaded by the optical module interface of the four channels, first performs serial-to-parallel conversion and uniformly converts it into data with a bit width of 32 bits, then parses out the valid audio and video data and data ID according to the custom message format, and sends the valid audio and video data and data ID to the cache control module.

[0031] Specifically, the custom protocol processing module extracts the clock for the received data, the number of channels can be configured according to the bandwidth requirements, the user data width is consistent with the output port width of the interface selection module, and is decoded according to the Aurora 64B66B format. It is transmitted to the inside of the FPGA module across the clock domain through the asynchronous FIFO. According to the type of message received, the FPGA will parse the data at the protocol layer, and finally obtain valid audio and video data after parsing, calculation, extraction and other operations, and input the data into the cache control module.

[0032] Specifically, Figure 2As shown, in this embodiment, the custom protocol processing module includes 4 serial input channels, namely data_in0, data_in1, data_in2, data_in4 and one input clock clk_in, with a clock frequency of 100MHz. The above 4 serial input channels receive the audio and video data uploaded by the 4 channels of the optical module interface, first perform serial-to-parallel conversion, and uniformly convert them into parallel data with a bit width of 32 bits. The data of all 4 channels are collected and spliced ​​into 128-bit parallel data, and at the end of a complete data cycle, the data valid signal valid is pulled high, and the 128-bit data is output at the data interface data_out[127:0] and the 8-bit data ID is output at the data ID interface id_out[7:0] synchronously through the clk_out clock signal.

[0033] The cache control module caches the audio and video data uploaded by the custom protocol processing module to DDR4 through the AXI bus, and sends the audio and video data to be processed in DDR4 to the data encryption module;

[0034] Specifically, DDR4 is managed by the MIG controller. MIG can greatly simplify the DDR operation timing. The complicated DDR physical interface timing has been integrated into the IP. Only the AXI bus of the IP needs to be operated, saving development time.

[0035] The key management module generates a key for data encryption through the SM2 algorithm and sends the key to the cache register of the data encryption module;

[0036] Specifically, the key management module generates a 128-bit random key through a random number generation algorithm, and reads a 128-bit public key from the FLASH memory. It uses the SM2 algorithm to encrypt the random key with the 128-bit public key read from the FLASH memory to obtain the key used for the final encrypted data, thereby ensuring the security of the key.

[0037] The data encryption module performs hardware encryption processing on the audio and video data to be processed by the SM4 algorithm module to obtain the encrypted data ciphertext.

[0038] The HDMI output interface module converts the encrypted audio and video data into HDMI format according to the HDMI 2.0 protocol and outputs it at the HDMI TX interface.

[0039] Specifically, the HDMI output interface module is implemented using Xilinx's HDMI TX Subsystem IP, which includes the video data interface Video Interface (AXI4-Stream / Native Video), the audio data interface AudioInterface (AXI4-Stream), the CPU control interface CPU Interface (AXI4-Lite), three interface signals from the PHY Layer (Link clock, Link data, Video clock) and some other information interfaces. When instantiating the HDMI TXSubsystem IP, you can set some parameters in the Vivado Integrated Design Environment (IDE). For example, select AXI4-Stream for the video interface.

[0040] like Figure 3 As shown, it is a process of the coordinated work of each sub-module inside the FPGA module of the present invention. The various sub-modules inside the FPGA module cooperate to complete the process of reading, caching, encrypting, and outputting audio and video data messages, including the following steps:

[0041] Step S1, initializing each submodule: custom protocol processing module, cache control module, key management module and data encryption module;

[0042] Step S2, the custom protocol processing module receives and parses the custom audio and video messages uploaded by the optical receiving module interface, and uploads the parsed valid audio and video messages to the cache control module;

[0043] Step S3, the cache control module caches the valid audio and video data into DDR4 and waits for subsequent processing;

[0044] Step S4, the key management module generates a 128-bit random key and reads the 128-bit public key stored in FLASH;

[0045] Step S5, the key management module generates a key used for final data encryption through the SM2 algorithm;

[0046] Step S6, the key management module sends the final key to the cache register of the data encryption module to wait for subsequent processing;

[0047] Step S7, the data encryption module receives the audio and video data to be processed uploaded by the cache control module;

[0048] Step S8, the data encryption module performs hardware encryption processing on the audio and video data to be processed and the final key through the SM4 algorithm module to obtain the encrypted data ciphertext;

[0049] Step S9, the HDMI output interface module converts the key and the ciphertext into HDMI format;

[0050] In step S10, the HDMI TX interface outputs the encrypted audio and video data, completing the encrypted transmission of the audio and video data from the optical module interface to the HDMI TX interface, thereby ensuring the security and efficiency of high-speed audio and video data transmission.

[0051] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A system and method for high-speed audio and video data encryption based on FPGA, the architecture of which is: including an optical module interface, an FPGA module, a DDR4, a FLASH and an HDMI TX interface; the FPGA module internally includes a custom protocol processing module, a cache control module, a key management module and a data encryption module; The optical module interface receives audio and video data in a user-defined format, and the specific audio and video transmission format is flexibly determined by the application scenario and the protocol standard used; The DDR4 caches audio and video data in a custom format; The custom protocol processing module receives the audio and video data uploaded by the optical module interface of the four channels, first performs serial-to-parallel conversion, uniformly converts it into data with a bit width of 32 bits, and then parses out the valid audio and video data and data ID according to the custom message format, and sends the valid audio and video data and data ID to the cache control module; The cache control module caches the audio and video data uploaded by the custom protocol processing module to DDR4 through the AXI bus, and sends the audio and video data to be processed in DDR4 to the data encryption module; The key management module generates a key for data encryption through the SM2 algorithm and sends the key to the cache register of the data encryption module; The data encryption module performs hardware encryption processing on the audio and video data to be processed by the SM4 algorithm module to obtain the encrypted data ciphertext; The HDMI output interface module converts the encrypted audio and video data into HDMI format according to the HDMI 2.0 protocol and outputs it at the HDMI TX interface.

2. According to the system and method for high-speed audio and video data encryption based on FPGA in claim 1, its architecture is: The custom protocol processing module generates a message according to the custom protocol, including 4 serial input channels, namely data_in0, data_in1, data_in2, data_in4, input clock clk_in, data valid signal valid, output clock clk_out, data interface data_out[127:0] and data ID interface id_out[7:0]. When the valid signal is high, the data is valid, and the custom protocol processing module outputs 128-bit data at the data interface data_out[127:0] and 8-bit data ID at the data ID interface id_out[7:0] synchronously with the clk_out clock signal.

3. A system and method for high-speed audio and video data encryption based on FPGA, wherein the submodules inside the FPGA module cooperate to complete the process of reading, caching, encrypting, and outputting audio and video data messages, comprising the following steps: Step S1, initializing each submodule: custom protocol processing module, cache control module, key management module and data encryption module; Step S2, the custom protocol processing module receives and parses the custom audio and video messages uploaded by the optical receiving module interface, and uploads the parsed valid audio and video messages to the cache control module; Step S3, the cache control module caches the valid audio and video data into DDR4 and waits for subsequent processing; Step S4, the key management module generates a 128-bit random key and reads the 128-bit public key stored in FLASH; Step S5, the key management module generates a key used for final data encryption through the SM2 algorithm; Step S6, the key management module sends the final key to the cache register of the data encryption module to wait for subsequent processing; Step S7, the data encryption module receives the audio and video data to be processed uploaded by the cache control module; Step S8, the data encryption module performs hardware encryption processing on the audio and video data to be processed and the final key through the SM4 algorithm module to obtain the encrypted data ciphertext; Step S9, the HDMI output interface module converts the key and the ciphertext into HDMI format; In step S10, the HDMI TX interface outputs the encrypted audio and video data, completing the encrypted transmission of the audio and video data from the optical module interface to the HDMI TX interface, thereby ensuring the security and efficiency of high-speed audio and video data transmission.

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