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Method for creating file containing aerial effect information

A technology of information files and antenna effects, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as inability to extract CLF, error-prone, time-consuming, etc., achieve small time, save time, and realize the process simple effect

Inactive Publication Date: 2009-01-07
IPGOAL MICROELECTRONICS (SICHUAN) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] For relatively large designs, such as large analog IP, when manually generating CLF files, it is necessary to specifically calculate the area of ​​the conductors connected to each port, which is time-consuming and error-prone; for generating CLF provided by automatic layout and routing tools method, there is also a time-consuming problem, because none of these tools can directly extract CLF from the layout

Method used

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  • Method for creating file containing aerial effect information

Examples

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Embodiment 1

[0021] Such as figure 1 As shown, a method of generating a file containing antenna effect information, first generates a GDSII file from the edited layout, then runs the GDSII file through a layout verification tool to generate a file containing connection information, and finally converts the file containing connection information The connection information in is written to the CLF file.

[0022] The layout is a graphical representation of circuits in integrated circuit design, and is a bridge connecting integrated circuit design and integrated circuit manufacturing.

[0023] The file in the GDSII format is a graphics file of the layout of the integrated circuit, and is a file in binary form, and most layout verification tools support files in this format. In layout editing tools (such as Virtuoso, Laker, and L-edit, etc.), the GDSII file of the edited integrated circuit layout can be directly generated through the built-in functions of the layout editing tool.

[0024] In ...

Embodiment 2

[0031] In the layout editing environment of Laker (the layout editing tool of Silicon canvas company), a GDSII file is generated from the already drawn layout.

[0032] Write a file that extracts metal lines, polysilicon lines, and diffusion area information from a GDSII file. In this example, Caliber (Mentor's layout verification tool) is used to write the run file required for extraction in the syntax of Caliber, and then run Hercules to generate a file containing metal Files with information about lines, polysilicon lines, and diffusion areas.

[0033]In this example, AWK (a scripting language) is used under the LINUX system to write a script that can generate a fixed-format CLF file from the file obtained in step 2. After running the script, the required CLF file can be obtained. In this example The generated CLF file is a CLF file used in Soc Encounter (Candence's automatic placement and routing tool).

Embodiment 3

[0035] In Virtuoso (Cadence company's layout editing tool) layout editing environment, generate GDSII files from the already drawn layout.

[0036] Write a file that extracts metal lines, polysilicon lines, and diffusion area information from a GDSII file. In this example, Hercules (Synopsys' layout verification tool) is used to write the run file required for extraction in Hercules syntax, and then run Hercules to generate a file containing metal Files with information about lines, polysilicon lines, and diffusion areas.

[0037] In this example, PERL (a scripting language) is used under the LINUX system to write a script that can generate a fixed-format CLF file from the file obtained in step 2. After running the script, the required CLF file can be obtained. In this example The generated CLF file is a CLF file used in Astro (automatic placement and routing tool from Synopsys).

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Abstract

The invention discloses a method for generating files containing the antenna effect information, which is characterized in that: at first, a GDSII file is generated from a layout; then the GDSII file is operated by a layout verification tool to generate files containing the information of connecting lines; at last, the information of the connecting lines in the files which contain the information of the connecting lines is written into a CLF file. By using the layout verification tool and script language, the method provided by the invention can directly extract the CLF file with a simple process of realization, thus greatly saving time of editing engineers of integrated circuit layouts and saving cost on the design of the integrated circuit layouts; the method can also generate needed CLF files rapidly with respect to varied locating and wiring tools, thus providing great convenience for entering varied locating and wiring tools needed by the same IP; for integrated circuit layouts of varied projects, an operation file and a script program file complied last time can be adopted, thus reducing time of editing engineers of integrated circuit layouts to the minimal during the process of generation of the CLF files.

Description

technical field [0001] The invention relates to the field of integrated circuit back-end design, in particular to a method for generating files containing antenna effect information. Background technique [0002] In the manufacturing process of integrated circuit chips, floating metal lines or polysilicon conductors will collect charges like antennas during the process (such as plasma etching). When the metal line or polysilicon conductor has a large total length and is directly connected to the polysilicon gate, as the accumulated charge accumulates, the voltage also increases, and it is possible to break down the thin gate oxide layer. This phenomenon is called antenna effect. Usually, we use "antenna ratio" ("antenna ratio") to measure the probability that a chip can have antenna effect. The definition of "antenna ratio" is: the ratio of the area of ​​the conductor (usually a metal or polysilicon connection) constituting the so-called "antenna" to the area of ​​the gate...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 郭雨来邹铮贤
Owner IPGOAL MICROELECTRONICS (SICHUAN) CO LTD
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