48results about How to "Reduce antenna effect" patented technology

The invention provides a capacitive distance sensor. The capacitive distance sensor is on the basis of the physical principle that the value of a capacitor is inversely proportional to the distance between capacitor plates; and once a coupling capacitor is generated between the surface of a detected conductor and a capacitance measuring plate on the single side of the surface of a sensor, the distance from the capacitance measuring plate to the surface of the detected conductor can be calculated by measuring the value of the coupling capacitor. The capacitive distance sensor provided by the invention has a circuit structure, and comprises the capacitance measuring plate, a reference capacitor, a capacitor coupling plate, a reference capacitor charging circuit, a capacitance measuring plate discharging circuit, a charge neutralization circuit, a programmable level generator 1, a programmable level generator 2 and a voltage comparator. The capacitive distance sensor has the characteristics of linearization, resistance to shifting, and low noise.

In the present invention, a seismic receiver contains an onboard digitizer that samples and converts a signal from detected seismic energy into the digital domain. The receiver contains an analog to digital converter, a transmission circuitry, and a link to the seismic detection circuitry. The signal from the seismic detection circuitry is converted into a digital signal, which is then relayed to the data recorder. These components are all resident to the receiver itself. Additional control circuitry is employed to provide clocking and testing functions. These receivers communicate with one another, and provide sampled seismic data on an individual basis. The components may be prepared on a PCB and put inside the receiver cap. The PCB may be flexible in nature, as to provide a maximum of surface mounted components in the smallest amount of space.

A semiconductor package includes a lead frame (2) comprising a chip position (4) and a plurality of lead fingers (3). Each lead finger (3) includes a incision (19) in an inner edge providing a chip recess (25). The semiconductor package (12) further includes a semiconductor chip (10) locating in the chip recess (25). The semiconductor chip (10) is arranged with an active surface (17) with a plurality of chip contact pads (16) on each of which an electrically conductive bump (11) is disposed. The inner portions (13) of the lead fingers (3) protrude into the chip position (4) and are electrically connected to the chip contact pads (16) by electrically conductive bumps (11).

The invention discloses a leaky-wave dual-antenna system comprising a transmitting antenna array and a receiving antenna array. The transmitting antenna array comprises plural first microstrips and plural corresponding first differential circuits, and each of the first differential circuit matches the corresponding first microstrip by a L-type matching network; the receiving antenna array comprises plural second microstrips and plural corresponding second differential circuits, and each of the second differential circuit matches the corresponding second microstrip by a L-type matching network. A first end and a second end of each of the first differential circuits are respectively connected to the corresponding first microstrip; a third end and a fourth end of each of the second differential circuits are respectively connected to the corresponding second microstrip.

The invention provides an integrated circuit, a chip bonding pad structure and a manufacture method. The chip bonding pad comprises a main bonding pad and a ring bonding pad. In a process of fabricating charges comprising formation of the chip bonding pad, a grid of a metal oxide semiconductor transistor in a substrate of the integrated circuit is electrically connected with the ring bonding pad,therefore area ratio from an antenna to the grid is less than a proportion of a given antenna, thus effectively reducing or avoiding antenna effect. The main bonding pad is electrically coupled with the ring bonding pad through a metal bridge formed in an upper inside cable metal layer or an uppermost conductive bonding pad layer. The chip bonding pad provided by the invention is a probe bonding pad on a parameter testing line or a bonding pad on the integrated circuit.

An embodiment of an electronic signal amplifier comprises a power source, an input inductor, an output inductor and one or more branches connected in parallel between the terminals of the power source. Each branch comprises a transistor having a control electrode connected to an intermediate terminal of the input inductor, a first main electrode connected to a first terminal of the power source, and a second main electrode connected to a second terminal of the power source via a capacitor. The second main electrode of each transistor of a branch is also connected to an intermediate terminal of the output inductor.

The invention discloses a data line and electronic equipment. The data line comprises an AM connector, a Type C connector, a connecting line and at least one capacitor, the two ends of the connecting line are electrically connected with the AM connector and the TypeC connector respectively, the connecting line comprises an aluminum foil used for shielding electromagnetic waves, and a containing space is formed in the inner side of the aluminum foil; the two power lines, the two signal lines and the two inner ground lines are arranged in the accommodating space on the inner side of the aluminum foil; the outer ground wire is arranged on the outer side of the aluminum foil; the power line is used for providing power, and the signal line is used for transmitting USB signals; the inner ground wire is arranged between the two signal wires and connected with the two signal wires and the inner side of the aluminum foil, and the inner ground wire is used for providing backflow for the power supply and providing reference ground for the signal wires; the outer ground wire is connected with the outer side of the aluminum foil and the metal shell of the AM connector; and the at least one capacitor is used for introducing electromagnetic waves coupled to a metal shell of the Type C connector to a ground wire.

The invention discloses a BSI process deep trench isolation manufacturing method. The method comprises the following steps: conducting etching to form deep trench isolation, then depositing metal witha first preset thickness, fully filling the deep trench isolation, and forming covering layers on the surface and two sides of the deep trench isolation; removing a part of the covering layers with asecond preset thickness by grinding; and conducting etching to remove the residual covering layers by adopting an etching process with an adjustable wafer in-plane etching rate, and only reserving metal filling in the deep trench isolation. According to the invention, the in-plane uniformity of the wafer can be improved, and the problem of insufficient wafer edge windows is solved; and the metalon the surface of the deep trench isolation is removed in two steps, and the size of the metal on the top of the deep trench isolation can be adjusted, so antenna effect is reduced, and RTS is reduced.

The invention relates to the technical field of electronics and particularly relates to a method for solving antenna effect of a cooling fin. The method comprises the steps of S1, providing an integrated chip and setting a heat conduction layer and a metal cooling fin on the integrated chip in sequence; and S2, adjusting thickness of the heat conduction layer to be unequal to a preset value, thereby reducing the antenna effect of the metal cooling fin. The technical scheme provided by the invention has the beneficial effects that an electromagnet interference method for solving the antenna effect is disclosed; the thickness of the heat conduction layer is adjusted to be unequal to the preset value, so the antenna effect of the metal cooling fin is reduced; a designer is assisted to designan H-shaped heat sink with low radiation; and an engineer is assisted to analyze an EMI (Electromagnet Interference) radiation problem of an electronic product.

The invention discloses a filtering antenna for wearable devices, which includes a top dielectric substrate, a bottom dielectric substrate, an antenna radiation unit, a top metal ground, a bottom metal ground, and an artificial magnetic conductor structure. The antenna radiation unit is printed on an upper surface of the top dielectric substrate, the top metal ground is printed on a lower surface of the top dielectric substrate, the artificial magnetic conductor structure is etched on an upper surface of the bottom dielectric substrate, and the bottom metal ground is printed on a lower surface of the bottom dielectric substrate. The antenna radiation unit is formed by a circular patch and a microstrip coupling feed stub structure. The invention has the advantages of miniaturization, easy integration, low profile, high gain, anti-interference, may work in the 5.8-GHz ISM frequency band, may be used in wearable devices, has filtering effect etc., and is suitable in the field of human body wireless local area network communications.

A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.