Low-orbit satellite-borne digital logic anomaly inspection method and navigation baseband chip

Abstract

The invention discloses a low-orbit satellite-borne digital logic anomaly inspection method and a navigation baseband chip. Comprising the following steps: setting a corresponding verification data set and a configuration item for each digital logic unit; setting timing duration to inspect each digital logic unit in the chip at fixed time; judging whether the current polled digital logic unit is idle or not, if so, continuing to execute the subsequent steps, otherwise, switching to the next digital logic unit to continue polling; obtaining a verification data set and a configuration item corresponding to the current digital logic unit; configuring according to the configuration item, and sending standard data into a digital logic unit for starting to obtain feature data; judging whether the feature data is consistent with expected data or not, and if yes, judging that the digital logic unit works normally; if not, judging that the digital logic unit is abnormal; and repairing and reconfiguring the digital logic unit which is judged to be abnormal. According to the scheme of the invention, independent detection and anomaly repair of each digital logic unit can be realized, and the method is more targeted.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technologies, and in particular, to a method for abnormally inspecting digital logic of a low-earth orbit satellite-borne and a navigation baseband chip. Background Art

[0002] Due to advantages such as low orbital altitude, strong signal power, and low construction cost, low-earth orbit satellites have received extensive attention and applications in recent years. Because the constellation configuration of low-earth orbit satellites changes rapidly and the coverage range of a single satellite is much smaller than that of high-earth orbit satellites, low-earth orbit constellations often consist of hundreds or even thousands of satellites. How to quickly and efficiently complete orbit determination for satellites has become one of the research hotspots. Low-earth orbit satellites equipped with Beidou navigation receivers will have richer satellite orbit determination means. However, the Beidou navigation receiver or the core baseband chip needs to have the ability to work normally in the low-earth orbit space and needs to cope with space radiation, single-event upset effects, etc. At the same time, in the navigation field itself, the trend of using low-earth orbit satellites to broadcast navigation enhancement signals or communication-navigation integrated signals is becoming more and more obvious. In the future, low-earth orbit satellite payloads in the communication-navigation integration field will have the on-board Beidou navigation ability and the transceiver ability of enhanced communication-navigation signals. Considering that digital circuits, storage units, etc. in satellite-borne payloads are all affected by radiation and single-event upsets, higher requirements are put forward for the performance stability of the baseband for satellite-borne Beidou navigation and communication-navigation integration processing. We need to improve the space radiation resistance of core digital basebands such as the navigation receiver baseband and the communication-navigation integration processing baseband, as well as the recognition ability when single-event upsets occur abnormally. Therefore, it is particularly important to propose a targeted abnormal detection method for problems such as single-event upsets and logic anomalies in low-earth orbit satellite-borne digital chips. Summary of the Invention

[0003] To solve the above technical problems, embodiments of the present invention provide a method for abnormally inspecting digital logic of a low-earth orbit satellite-borne and a navigation baseband chip.

[0004] The technical solution of the embodiments of the present invention is realized as follows: Embodiments of the present invention provide a method for abnormally inspecting digital logic of a low-earth orbit satellite-borne, the method including: Step S1: For each digital logic unit in the chip, set a corresponding verification data set and configuration items; the verification data set includes standard data and expected data; the standard data is used to test whether the corresponding digital logic unit can work normally; the expected data is the output result obtained after processing the standard data when the digital logic unit works normally; the configuration items are the configuration contents required for the digital logic unit to work normally; Step S2: Set a timing duration, and regularly inspect each digital logic unit in the chip; determine whether the currently inspected digital logic unit is idle. If it is idle, continue to execute Step S3; otherwise, switch to the next digital logic unit and continue the inspection; Step S3: Obtain the check data set and configuration items corresponding to the digital logic unit currently inspected; configure the digital logic unit according to the configuration items, and send the standard data in the check data set into the digital logic unit to start it, and obtain the characteristic data output by the digital logic unit; Step S4: Determine whether the characteristic data is consistent with the expected data. If it is consistent, it is determined that the digital logic unit is working properly; if it is inconsistent, it is determined that the digital logic unit has an abnormality; Step S5: Repair and reconfigure the digital logic unit determined to have an abnormality.

[0005] In one embodiment, the digital logic units in the chip include a capture engine, a tracking engine, a TURBO channel decoder, and a VITERBI channel decoder.

[0006] In one embodiment, the configuration items of the capture engine are 1 ms of coherent integration, 1 non-coherent time, 3 frequency windows, a center frequency of 0 Hz, and a code rate fc consistent with the frequency point where the check data is located; the standard data of the capture engine is 2 ms of Beidou B1I frequency point intermediate frequency data; the expected data of the capture engine is the peak amplitude, phase, and frequency results calculated by the normal operation of the capture engine; The configuration items of the tracking engine are 1 ms of coherent integration, a center frequency of 0 Hz, a code rate fc consistent with the frequency point where the check data is located, and a code start phase of 0; the standard data of the tracking engine is 2 ms of Beidou B1I frequency point intermediate frequency data; the expected data of the tracking engine is the coherent integration results of the IQ channels calculated by each correlator calculated by the normal operation of the tracking engine; The configuration items of the TURBO channel decoder are to configure and start TURBO decoding with the length of the data to be decoded being L and the number of iterations being 3 times; the standard data of the TURBO channel decoder is the soft information data to be decoded with a length of L; the expected data of the TURBO channel decoder is the correct decoded result bit information; The configuration items of the VITERBI channel decoder are to configure and start VITERBI decoding with the length of the data to be decoded being M and the truncation mode; the standard data of the VITERBI channel decoder is the soft information data to be decoded with a length of M; the expected data of the VITERBI channel decoder is the correct decoded result bit information.

[0007] In one embodiment, determining whether the digital logic unit currently inspected is idle includes: For the capture engine, if the logic module of the capture engine is performing normal capture processing or inspection and verification processing at the current moment, it is determined that the capture engine is in a busy state; if the logic module of the capture engine is not performing any processing at the current moment, it is determined that the capture engine is in an idle state; For the tracking engine, if the logic module of the tracking engine is performing normal tracking processing or inspection and verification processing at the current moment, it is determined that the tracking engine is in a busy state; if the logic module of the tracking engine is not performing any processing at the current moment, it is determined that the tracking engine is in an idle state; For the TURBO channel decoder, if the logic module of the TURBO channel decoder is performing normal decoding calculation or inspection and verification calculation at the current moment, it is determined that the TURBO channel decoder is in a busy state; if the logic module of the TURBO channel decoder is not performing any processing at the current moment, it is determined that the TURBO channel decoder is in an idle state; For the VITERBI channel decoder, if the logic module of the VITERBI channel decoder is performing normal decoding calculation or inspection and verification calculation at the current moment, it is determined that the VITERBI channel decoder is in a busy state; if the logic module of the VITERBI channel decoder is not performing any processing at the current moment, it is determined that the VITERBI channel decoder is in an idle state.

[0008] In one embodiment, repairing and reconfiguring the digital logic unit determined to have an abnormality includes: If the abnormal digital logic unit is the capture engine, globally reset all logic modules of the capture engine, reconfigure the registers, and overwrite and clear the data RAM; If the abnormal digital logic unit is the tracking engine, locally reset the abnormal sub-tracking channels in the logic module of the tracking engine and reconfigure the registers; If the abnormal digital logic unit is the TURBO channel decoder, globally reset the TURBO channel decoder, reconfigure the registers, and reconfigure the turbo interleaving table; If the abnormal digital logic unit is the VITERBI channel decoder, globally reset the VITERBI channel decoder and reconfigure the registers.

[0009] In one embodiment, before repairing and reconfiguring the digital logic unit determined to have an abnormality, the method further includes: If the abnormal digital logic unit is the capture engine, perform abnormal inspection on the capture engine to re-determine the abnormal situation of the capture engine; If the abnormal digital logic unit is the tracking engine, perform abnormal inspection and partial triple modular redundancy detection on the tracking engine to re-determine the abnormal situation of the tracking engine; If the abnormal digital logic unit is a TURBO channel decoder, perform an abnormal inspection on the TURBO channel decoder to determine the abnormal situation of the TURBO channel decoder again; If the abnormal digital logic unit is a VITERBI channel decoder, perform an abnormal inspection on the VITERBI channel decoder to determine the abnormal situation of the VITERBI channel decoder again.

[0010] In one embodiment, the set timing duration is 100 ms.

[0011] An embodiment of the present invention further provides a navigation baseband chip, including: a processor and a memory for storing a computer program that can run on the processor; wherein, when the processor is used to run the computer program, it executes the steps of the above-mentioned method.

[0012] The solution of this embodiment has the following beneficial effects: This embodiment utilizes the advantages of the area and computing power of the ASIC special chip to provide a method for monitoring single-event upsets in a digital baseband chip with low cost and low false alarms. According to the characteristics of the unit to be detected, a test data set and configuration items are customized. When dealing with an abnormality, only the problematic unit needs to be repaired, which is more targeted, reduces the influence range of the abnormal point, and has higher efficiency. Description of the Drawings

[0013] Figure 1 It is a schematic flowchart of the method for abnormal inspection of low-orbit spaceborne digital logic in an embodiment of the present invention; Figure 2 It is a schematic diagram of the abnormal inspection process of the TURBO channel decoder in an embodiment of the present invention; Figure 3 It is an internal structure diagram of a computer device in an embodiment of the present invention. Detailed Embodiment

[0014] The present invention will be further described in detail below in conjunction with the drawings and embodiments.

[0015] An embodiment of the present invention provides a method for abnormal inspection of low-orbit spaceborne digital logic, as Figure 1 shown, the method includes: Step S1: For each digital logic unit in the chip, set corresponding test data sets and configuration items; the test data sets include standard data and expected data; the standard data is used to test whether the corresponding digital logic unit can work normally; the expected data is the output result obtained after processing the standard data when the digital logic unit works normally; the configuration items are the configuration contents required for the digital logic unit to work normally; Step S2: Set the timing duration and periodically inspect each digital logic unit in the chip; determine whether the currently inspected digital logic unit is idle. If it is idle, proceed to step S3; otherwise, switch to the next digital logic unit and continue the inspection. Step S3: Obtain the check data set and configuration items corresponding to the currently inspected digital logic unit; configure the digital logic unit according to the configuration items, send the standard data in the check data set into the digital logic unit to start it, and obtain the characteristic data output by the digital logic unit. Step S4: Determine whether the characteristic data is consistent with the expected data. If they are consistent, it is determined that the digital logic unit is working properly; if they are inconsistent, it is determined that the digital logic unit has an abnormality. Step S5: Repair and reconfigure the digital logic unit determined to have an abnormality.

[0016] In this embodiment, a targeted anomaly detection method is proposed for problems such as single-event upsets and logic anomalies in the on-board digital chips of low-earth orbit satellites, and a Beidou navigation baseband chip is designed based on this method. Different from the traditional FPGA-based on-board digital logic single-event upset detection means, the method of this embodiment is based on a digital application-specific integrated circuit (ASIC), and uses the area and main frequency advantages of the ASIC to perform customized anomaly detection measures for each dedicated digital logic unit, subsystem, or accelerator module in the chip, etc., with the characteristics of strong pertinence, easy implementation, and extremely low false alarm rate of detection.

[0017] Specifically, in step S1, the check data set and configuration items of the digital logic units in the chip are customized. Here, the digital logic unit refers to a logic module, logic subsystem, dedicated operation accelerator, etc. that can complete specific functions such as control and calculation. Such digital logic units include (but are not limited to) registers, RAM, hardwired logic, state machines, etc. In actual applications, the digital logic units may include a capture engine, a tracking engine, a TURBO channel decoder, and a VITERBI channel decoder.

[0018] Here, the check data set refers to the standard input data used to test whether the digital logic unit is working properly, and the expected result output data that should be obtained after the digital logic unit processes the standard input data. Here, the configuration items refer to the configuration content required for the digital logic unit to meet the current job function or work properly, including but not limited to working mode, algorithm implementation parameters, input configuration, output configuration, etc.

[0019] Both the check data set and the configuration items can be stored in a storage unit with ECC data verification, better radiation resistance process technology, etc., and triple modular redundancy reinforcement is performed, such as a flash unit.

[0020] The following is a list of verification data sets and configuration items for core digital logic units such as the acquisition engine (AE), tracking engine (TE), TURBO channel decoder, and VITERBI channel decoder in the navigation baseband chip: Table 1 In step S2, the spaceborne baseband chip creates a timed inspection task and performs an inspection every timed period, thereby cyclically traversing all chip digital logic units to be verified; the default value (the value after reset) of the timed period is hardwired and solidified inside the chip.

[0021] During the timed inspection, it is judged whether the currently inspected chip digital logic unit X is idle, that is, whether it is running. If it is idle, the process continues to the next step to detect this chip digital logic unit. If it is busy, it switches to the next chip digital logic unit Y and continues the query; Here, the idle and busy flags of the chip digital logic unit can be set, which are generated by the target chip digital logic unit to be inspected. If the currently inspected target chip digital logic unit is working, the busy flag is valid and the idle flag is invalid; otherwise, if the currently inspected target chip digital logic unit is not working, the idle flag is valid and the busy flag is invalid; the said busy flag and idle flag.

[0022] The preferred generation conditions for typical core digital logic units such as the acquisition engine (AE), tracking engine (TE), TURBO channel decoder, and VITERBI channel decoder in the navigation baseband chip are shown in the following table: Table 2 In step S3, the spaceborne baseband chip selects the verification data set adapted to X from the verification data set customized in S1, extracts the standard data S_X and the expected data R_X of the corresponding processing result, where R_X is the expected generation result after S_X is sent into the logic unit X; the verification data set and configuration items are hardwired and solidified inside the chip, and the data content is customized and generated according to the functional characteristics of the logic unit X during the chip design phase.

[0023] The spaceborne baseband chip sends the standard data S_X into the logic unit X and starts it. After the logic unit X processes the data, a characteristic output result (characteristic data) is obtained; when designing the chip digital logic unit, a circuit for generating characteristic data is added.

[0024] In step S4, after obtaining the characteristic data of the logic unit X, it is sent to the expected judgment device for verification to determine whether the actually generated characteristic data is consistent with the expected data R_X. If they are consistent, it can be considered that the detection result of the logic unit under the detection method of the present invention is normal. This can significantly improve the system's confidence in the logic unit. At the system level, combined with classic triple modular redundancy and logic unit redundancy detection in the industry, the confidence level can be further improved.

[0025] If the characteristic data is inconsistent with the expected data, it is determined that an abnormality has occurred inside the logic unit X being currently inspected; if the characteristic data is inconsistent with the expected data, it can be determined that an abnormality has occurred in the logic unit X or its surrounding logic, and the system needs to perform repair processing on the logic unit.

[0026] In step S5, soft repair and reconfiguration are performed on the abnormal logic unit module. For typical core digital logic units such as the acquisition engine (AE), tracking engine (TE), TURBO channel decoder, and VITERBI channel decoder in the navigation baseband chip, after an abnormality is detected during their inspection, the preferred monitoring mechanism and repair method are as shown in the following table: Table 3 The method of this embodiment can cyclically perform abnormal inspection on core digital logic units such as the acquisition engine (AE), tracking engine (TE), TURBO channel decoder, and VITERBI channel decoder through a timed inspection task, and timely repair the faulty module after an abnormality occurs, effectively improving the stability and radiation resistance of the navigation baseband chip.

[0027] See Figure 2 , and the following will illustrate this solution with a specific embodiment.

[0028] S101: Formulate a data verification set for all key digital logic units in the low-earth orbit spaceborne baseband chip; for example, for the TURBO channel decoder, that is, the turbo(192,60) decoder, a group of 4-bit random noise soft information with a length of 192 can be designed as the standard data, and the configuration items are set to a code rate of 1 / 3, blocksize 60, 3 iterations, and 4-bit soft information. The standard data and configuration items are sent into the turbo(192,60) decoder, and the number of decoder iterations is configured as the default value of 8 times. The soft information result and decision result of the last iteration of SISO after being processed by the decoder are used as the expected data. The standard data, configuration items, and expected data form the data verification set; S201: The spaceborne baseband chip creates a timed inspection task, performs an inspection every 100 ms, and makes a judgment and processing on the currently inspected logic unit; among them, it is triggered every 100 ms and is implemented by hardwired curing inside the chip; S301: If the currently inspected turbo (192, 60) decoder is idle, continue to execute the next step; otherwise, switch to the next logic unit to continue querying; the query of the turbo decoder status requires adding a circuit for generating idle and busy flags when designing the chip digital logic unit; S401: The onboard baseband chip selects the verification data set and configuration items of the turbo (192, 60) decoder from the data verification set customized in step S1. It uses 1 / 3 code rate, blocksize 60, iterations 3 times, and 4 bits of soft information as the input configuration of the turbo (192, 60) decoder, and uses 4 bits of random noise soft information of length 192 as the standard data S_X. The expected data after the normal decoding of this set of data is used as R_X. The standard data and configuration items need to be hard-wired in the chip. S501: The onboard baseband chip transmits 4-bit random noise soft information of length 192 to the turbo (192, 60) decoder. The decoder processes the data and obtains real-time feature output results (feature data). The turbo decoder needs to add circuits to generate feature data during design. S601: Expected judgement verification, which is performed by comparing the expected data R_X obtained in step S4 with the feature data generated in real time in S5. If the data are consistent, it can be preliminarily considered that the turbo (192, 60) decoder is working normally. If necessary, the classic abnormal inspection method in the industry can be combined to further determine the single event upset of the current inspection logic unit X. S701: If the characteristic data is inconsistent with the expected data, it is determined that an abnormality must have occurred inside the turbo(192,60) decoder currently being inspected, such as a single event upset in the storage unit data; S801: Repair and reset the turbo (192, 60) decoder that has an abnormality, for example, reset the decoder and reinitialize the configuration parameters of the decoder.

[0029] The method of this embodiment has the following beneficial effects: 1. Leveraging the advantages of ASIC dedicated chip area and computing power, a low-cost, low-false-alarm single-event upset anomaly monitoring method for digital baseband chips is provided; 2. A method for independent testing of digital logic units (including subsystems or accelerators) on a chip is proposed. Based on the characteristics of the units being tested, the test data set and configuration items are customized. During exception handling, only the problematic units need to be repaired. This method is more targeted, reduces the impact of the anomaly, and is more efficient.

[0030] To implement the method of the embodiments of the present invention, the embodiments of the present invention further provide a navigation baseband chip, including: a processor and a memory for storing a computer program that can run on the processor; wherein, when the processor is used to run the computer program, it executes the steps of the above-mentioned method.

[0031] The above-mentioned navigation baseband chip provided in this embodiment and the above-mentioned method embodiment belong to the same concept. For the specific implementation process, please refer to the method embodiment and will not be elaborated here.

[0032] Based on the hardware implementation of the above program module, and to implement the method of the embodiments of the present invention, the embodiments of the present invention further provide an electronic device (computer device). Specifically, in one embodiment, the computer device may be a terminal, and its internal structure diagram may be as Figure 3 shown. The computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05, and a memory (not shown in the figure) connected through a system bus. Among them, the processor A01 of the computer device is used to provide computing and control capabilities. The memory of the computer device includes an internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 in the non-volatile storage medium A06. The network interface A02 of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor A01, it implements the method of any one of the above embodiments. The display screen A04 of the computer device may be a liquid crystal display screen or an electronic ink display screen, and the input device A05 of the computer device may be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the outer shell of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0033] Those skilled in the art can understand that Figure 3 the structure shown in

[0034] is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0035] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0036] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for realizing the specified functions in one Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0037] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means realizes the specified functions in one Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0038] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for realizing the specified functions in one Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0039] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and a memory.

[0040] The memory may include non-permanent memory in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash memory (flashRAM). The memory is an example of a computer-readable medium.

[0041] A computer-readable medium includes both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile discs (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer-readable medium does not include transitory computer-readable media such as modulated data signals and carrier waves.

[0042] It can be understood that the memory in the embodiments of the present invention can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM, Read-Only Memory), a programmable read-only memory (PROM, Programmable Read-Only Memory), an erasable programmable read-only memory (EPROM, Erasable Programmable Read-Only Memory), an electrically erasable programmable read-only memory (EEPROM, Electrically Erasable Programmable Read-Only Memory), a ferromagnetic random access memory (FRAM, ferromagnetic random access memory), a flash memory (Flash Memory), a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM, Compact Disc Read-Only Memory); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM, RandomAccess Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as a static random access memory (SRAM, Static Random Access Memory), a synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory), a dynamic random access memory (DRAM, Dynamic Random Access Memory), a synchronous dynamic random access memory (SDRAM, SynchronousDynamic Random Access Memory), a double data rate synchronous dynamic random access memory (DDRSDRAM, Double Data Rate Synchronous Dynamic Random Access Memory), an enhanced synchronous dynamic random access memory (ESDRAM, Enhanced Synchronous Dynamic Random Access Memory), a sync link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and a direct rambus random access memory (DRRAM, Direct Rambus Random Access Memory).The memories described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memories.

[0043] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising the element.

[0044] The above are only the embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A method for abnormal inspection of digital logic on low-earth orbit satellite-borne, characterized in that, The method includes: Step S1: For each digital logic unit in the chip, set a corresponding check data set and configuration items; the check data set includes standard data and expected data; the standard data is used to test whether the corresponding digital logic unit can work properly; the expected data is the output result obtained after processing the standard data when the digital logic unit works properly; the configuration items are the configuration contents required for the digital logic unit to work properly; Step S2: Set a timing duration and regularly inspect each digital logic unit in the chip; determine whether the currently inspected digital logic unit is idle. If it is idle, continue to execute Step S3; otherwise, switch to the next digital logic unit and continue the inspection; Step S3: Obtain the check data set and configuration items corresponding to the currently inspected digital logic unit; configure the digital logic unit according to the configuration items, and send the standard data in the check data set into the digital logic unit to start it, and obtain the characteristic data output by the digital logic unit; Step S4: Determine whether the characteristic data is consistent with the expected data. If it is consistent, it is determined that the digital logic unit works normally; if it is inconsistent, it is determined that the digital logic unit has an abnormality; Step S5: Repair and reconfigure the digital logic unit determined to have an abnormality.

2. The low-earth orbit spaceborne digital logic anomaly inspection and patrol method according to claim 1, wherein The digital logic units in the chip include a capture engine, a tracking engine, a TURBO channel decoder, and a VITERBI channel decoder.

3. The method for abnormal inspection of on-orbit digital logic of low-orbit satellites according to claim 2, wherein The configuration items of the capture engine are coherent integration for 1 ms, non-coherent for 1 time, 3 frequency windows, center frequency 0 Hz, and the code rate fc is the same as the frequency point where the check data is located; the standard data of the capture engine is 2 ms of Beidou B1I frequency point intermediate frequency data; the expected data of the capture engine is the peak amplitude, phase, and frequency results calculated when the capture engine works properly; The configuration items of the tracking engine are coherent integration for 1 ms, center frequency 0 Hz, the code rate fc is the same as the frequency point where the check data is located, and the code starting phase is 0; the standard data of the tracking engine is 2 ms of Beidou B1I frequency point intermediate frequency data; the expected data of the tracking engine is the IQ path coherent integration results calculated by each correlator when the tracking engine works properly; The configuration items of the TURBO channel decoder are to configure and start TURBO decoding with the length of the data to be decoded being L and the number of iterations being 3 times; the standard data of the TURBO channel decoder is the soft information data to be decoded with the length of L; the expected data of the TURBO channel decoder is the correct decoded result bit information; The configuration items of the VITERBI channel decoder are to configure and start VITERBI decoding with the length of the data to be decoded being M and the truncation mode; the standard data of the VITERBI channel decoder is the soft information data to be decoded with the length of M; the expected data of the VITERBI channel decoder is the correct decoded result bit information.

4. The low-orbit spaceborne digital logic anomaly patrol inspection method according to claim 3, wherein Determining whether the currently inspected digital logic unit is idle includes: For the capture engine, if the logic module of the capture engine is performing normal capture processing or patrol inspection verification processing at the current moment, it is determined that the capture engine is in a busy state; if the logic module of the capture engine is not performing any processing at the current moment, it is determined that the capture engine is in an idle state; For the tracking engine, if the logic module of the tracking engine is performing normal tracking processing or patrol inspection verification processing at the current moment, it is determined that the tracking engine is in a busy state; if the logic module of the tracking engine is not performing any processing at the current moment, it is determined that the tracking engine is in an idle state; For the TURBO channel decoder, if the logic module of the TURBO channel decoder is performing normal decoding calculation or patrol inspection verification calculation at the current moment, it is determined that the TURBO channel decoder is in a busy state; if the logic module of the TURBO channel decoder is not performing any processing at the current moment, it is determined that the TURBO channel decoder is in an idle state; For the VITERBI channel decoder, if the logic module of the VITERBI channel decoder is performing normal decoding calculation or patrol inspection verification calculation at the current moment, it is determined that the VITERBI channel decoder is in a busy state; if the logic module of the VITERBI channel decoder is not performing any processing at the current moment, it is determined that the VITERBI channel decoder is in an idle state.

5. The low-orbit spaceborne digital logic anomaly inspection method according to claim 2, wherein Repair and reconfigure the digital logic unit determined to have an abnormality, including: If the abnormal digital logic unit is the capture engine, globally reset all logic modules of the capture engine, reconfigure the registers, and overwrite and clear the data RAM; If the abnormal digital logic unit is the tracking engine, locally reset the abnormal sub-tracking channels in the logic module of the tracking engine and reconfigure the registers; If the abnormal digital logic unit is the TURBO channel decoder, globally reset the TURBO channel decoder, reconfigure the registers, and reconfigure the turbo interleaving table; If the abnormal digital logic unit is the VITERBI channel decoder, globally reset the VITERBI channel decoder and reconfigure the registers.

6. The method for anomaly inspection of on-orbit digital logic of low-earth orbit satellites according to claim 5, wherein, Before repairing and reconfiguring the digital logic unit determined to have an abnormality, the method further includes: If the abnormal digital logic unit is the capture engine, perform an abnormal patrol inspection on the capture engine to re-determine the abnormal situation of the capture engine; If the abnormal digital logic unit is the tracking engine, perform an abnormal patrol inspection and partial triple modular redundancy detection on the tracking engine to re-determine the abnormal situation of the tracking engine; If the abnormal digital logic unit is the TURBO channel decoder, perform an abnormal patrol inspection on the TURBO channel decoder to re-determine the abnormal situation of the TURBO channel decoder; If the abnormal digital logic unit is the VITERBI channel decoder, perform an abnormal patrol inspection on the VITERBI channel decoder to re-determine the abnormal situation of the VITERBI channel decoder.

7. The method for abnormal inspection of on-orbit digital logic of low-orbit satellites according to claim 1, characterized in that Set the timing duration to 100 ms.

8. A navigation baseband chip, characterized in that, Include: A processor and a memory for storing a computer program capable of running on the processor; wherein, when the processor is used to run the computer program, it executes the steps of the method according to any one of claims 1 to 7.

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