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111 results about "Packet-switching node" patented technology

A packet-switching node is a node in a packet-switching network that contains data switches and equipment for controlling, formatting, transmitting, routing, and receiving data packets. This article incorporates public domain material from the General Services Administration document "Federal Standard 1037C" (in support of MIL-STD-188).

Combined pipelined classification and address search method and apparatus for switching environments

A packet switching node having a pipelined packet processing architecture processing packets received via an input port associated with the packet switching node is presented. The method performed by the apparatus includes: determining a packet frame type of the packet received; selectively extracting packet header field values specific to a packet frame type, the extracted packet header field value including packet addressing information; ascribing to the packet a preliminary action to be performed in respect of the packet; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into one of a plurality of packet flows; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet in accordance with the switch response. Advantages are derived from: pipelined processing of packets which enables short-cutting the rest of the processing for improper packets; a flexible frame type determination which is fast for well know frame types yet flexible in support of new frame types delaying obsolescence of a particular implementation; an early determination of a processing action which is successively refined by subsequent stages; a combined Layer-2 and Layer-3 network addressing search engine operating on short bit length indexed Layer-2 and Layer-3 network addresses reducing network address table storage requirements, requiring a reduced data transfer bandwidth for network address table access, a large external hashed primary network address table, and a small internal secondary network address table; an early determination of a switch response; and packet-classification-based switch response and packet header modification.
Owner:SYNAPTICS INC

Distributing fault indications and maintaining and using a data structure indicating faults to route traffic in a packet switching system

Methods and apparatus are disclosed for distributing fault indications and maintaining and using a data structure indicating faults to route traffic in a packet switching system. In one embodiment, a packet switching system detects faults and propagates indications of these faults to the input interfaces of a packet switch, so the packet switch can adapt the selection of a route over which to send a particular packet. Faults are identified by various components of the packet switching system and relayed to one or more switching components to generate a broadcast packet destined for all input ports (i.e., to each I / O interface in a packet switch having folded input and output interfaces). Other embodiments, generate one or more multicast or unicast packets. The I / O interface maintains one or more data structures indicating the state of various portions of the packet switching system. In one embodiment, an output availability table is maintained indicating over which path a particular destination may be reached, as well as a link availability vector indicating which output likes of the input interface may be currently used. Using these as masks against possible routes in a fully functional system, the packet switching component (e.g., I / O interface) can identify which routes are currently available for reaching the destination of the received packet. These routes can then be selected between using one of numerous deterministic and non-deterministic methods.
Owner:CISCO TECH INC +1

Method and apparatus for using barrier phases to limit packet disorder in a packet switching system

Methods and apparatus are disclosed for using barrier phases to limit the disorder of packets which may be used in a computer or communications system. In one packet switching system, source nodes include an indication of their current barrier state in sent packets. For each barrier state, a predetermined range of sequence numbers may be used or a predetermined number of packets may be sent by a source node. The source, destination, and switching nodes are systematically switched between barrier phases, which is typically performed continuously in response to the flow of barrier request and barrier acknowledgement packets or signals. Each source node broadcasts to all forward connected nodes a barrier request to change to a next barrier state. After a switching node has received a barrier request on all incoming links, the switching node propagates the barrier request. Upon receiving barrier requests over all links, each destination stage relays an acknowledgement message to all connected source elements, which then send a barrier acknowledgement in much the same way, and each source element changes its barrier state causing the sequence number or counting space to be reset, and newly sent packets to indicate the new barrier state. Upon receiving all its barrier acknowledgement messages, each destination stage changes its barrier state, and then the destination can manipulate (e.g., resequence, reassemble, send, place in an output queue, etc.) packets marked with the previous barrier state as it knows that every packet from the previous barrier state has been received. This transition of barrier phases and limiting the number of packets sent per barrier phases may be used to limit the range of the sequence number space and the size of outgoing, resequencing, and reassembling buffers, as well providing a packet time-out mechanism which may be especially useful when non-continuous sequence numbers or time-stamps are included in packets for resequencing and / or reassembly purposes.
Owner:CISCO TECH INC

General flow table and method for supporting packet switching and circuit switching in SDN framework

The invention provides a general flow table and method for supporting packet switching and circuit switching in an SDN framework, and relates to the SDN framework in the information technology. The general flow table comprises a switching type domain, a circuit switching domain and a packet switching domain. The switching type domain comprises four marks of pure circuit switching, pure packet switching, circuit-packet switching and packet-circuit switching. Service flow is forwarded to a network controller of a control layer through a southbound interface. The network controller is used for judging the type and characteristics of the service flow, computing a forwarding path of the service flow and generating the corresponding general flow table. The network controller issues the general flow table to data forwarding equipment of a data layer through the southbound interface, and establishes corresponding forwarding rules in the data forwarding equipment. The service flow completes packet switching and circuit switching in the data forwarding equipment according to the forwarding rules. The general flow table and method can simultaneously support the packet switching technology and the circuit switching technology, and two existing basis independent networks can be replaced by a data and transmission convergent network efficient in operation.
Owner:WUHAN POST & TELECOMM RES INST CO LTD

Communication system and method capable of avoiding congestion in moving image data transmission

A communication system capable of avoiding congestion in transmission of moving image data, includes (1) at least one receiving terminal, (2) a moving image delivery device for delivering moving image data to the at least one receiving terminal, (3) a moving image conversion device which has at least one moving image conversion unit for converting, in accordance with conversion parameters, the moving image data sent from the moving image delivery device, a conversion parameter setting unit for determining the conversion parameters, and a monitored result receiving unit, and (4) at least one packet switching node which has at least one data storage unit for preliminarily storing the moving image data from the moving image conversion device to be sent to the at least one receiving terminal, a data amount monitor unit for monitoring an amount of the moving image data stored in the at least one data storage unit to judge that the monitored data amount reaches a first threshold, and a monitored result sending unit for sending a congestion preview information to the moving image conversion device when the data amount monitor unit judges that the monitored data amount reaches the first threshold. The monitored result receiving unit receives the congestion preview information from the monitored result sending unit, and the conversion parameter setting unit determines the conversion parameters so that the moving image conversion unit converts the moving image data sent from the moving image delivery device into a moving image data with a smaller coding bit rate.
Owner:KDDI R&D LAB INC

Ethernet switching method and device incorporating circuit switching and packet switching

The invention relates to a method for switching an Ethernet integrating circuit switching and packet switching, wherein an output slot of an output-port part of the Ethernet is divided according to unit transmission time of a fixed-length Ethernet frame and each output slot is flexibly appointed to participate the packet switching or a time division switching; after the input-port part of the Ethernet receives the fixed-length Ethernet frame, corresponding list items forwarded according to L2 / L3 of a switching unit is to switch the participate time division switching fixed-length Ethernet frame to the appointed slot of the appointed Ethernet port or to switch the participate packet switch ,the output-port part of the Ethernet port sends the fixed-length Ethernet frame according to serial number of the output slot under coordination of synchronization information. And a corresponding Ethernet switching device (500) consists of a switching unit (510), a forwarding table (520), at least two Ethernet ports (530) which are time-division multiplexed according to the unit transmission time of the fixed-length Entherent and a synchronization unit (540) used for keeping network synchronization.
Owner:北京紫光通信科技集团有限公司

Compact packet switching node storage architecture employing double data rate synchronous dynamic RAM

A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip/single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.
Owner:IKANOS COMMUNICATIONS
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