Processor system and interrupt response method

Abstract

The invention provides a processor system and an interrupt response method. In the processor system, an interrupt controller is used for setting the state of a control register, receiving an interrupt request signal which is sent from the outside and is used for requesting to execute an interrupt service program, setting the state of the control register to be a first state value when the interrupt request signal is received, and executing the interrupt service program after the interrupt server program is executed. Setting the state of the control register as a second state value; the multiplexer is used for reading the state value of the control register, when the read state value of the control register is a first state value, the multiplexer is communicated with the shadow register group and the arithmetic unit, and when the read state value of the control register is a second state value, the multiplexer is communicated with the main register group and the arithmetic unit; the main register group is used for storing data when the main program is operated; and the shadow register group is used for storing data when the interrupt server program runs. The delay in the interrupt response process can be reduced, and the system performance is improved.

Description

Technical Field

[0001] One or more embodiments of the present invention relate to the field of computer design, and more particularly to processor systems and interrupt response methods. Background Technology

[0002] In fields such as real-time control, embedded systems, and high-speed data acquisition, the processor's ability to respond quickly to asynchronous events is crucial, and interrupts are the primary mechanism for processors to respond to external events. An interrupt is when the CPU temporarily suspends the execution of the current program to handle a new situation. Specifically, during program execution, if a situation arises that the CPU must handle immediately, the process of the CPU temporarily suspending program execution to process this new situation is called an interrupt.

[0003] In the interrupt response method, the processor system needs to save the context, that is, execute multiple memory access instructions before the interrupt service routine is executed to save the data of the original task and avoid corrupting the data of the original task; and the processor system also needs to restore the context, that is, execute multiple memory access instructions after the interrupt service routine is executed to restore the data of the original task and continue to execute the original task.

[0004] In existing interrupt response methods, saving and restoring the context both require executing multiple memory access instructions. Since memory access is slow, this introduces significant latency, known as context switching overhead, which is a major bottleneck for high-performance real-time systems that require extremely low latency. Summary of the Invention

[0005] One or more embodiments of the present invention describe a processor system and an interrupt response method that can reduce latency in the interrupt response process and improve system performance.

[0006] According to a first aspect, a processor system is provided, the processor system comprising: an interrupt controller, a control register, a multiplexer, an arithmetic unit, a main register set, and a shadow register set;

[0007] The main register group and the shadow register group correspond one-to-one; one side of the multiplexer can be connected to either the main register group or the shadow register group, and the other side is connected to the arithmetic unit;

[0008] The interrupt controller is used to set the state of the control register, receive an interrupt request signal from the outside to request the execution of an interrupt service routine, set the state of the control register to a first state value when the interrupt request signal is received, and set the state of the control register to a second state value after the interrupt service routine is completed.

[0009] The multiplexer is used to read the status value of the control register. When the read status value of the control register is the first status value, the multiplexer connects the shadow register group and the arithmetic unit. When the read status value of the control register is the second status value, the multiplexer connects the main register group and the arithmetic unit.

[0010] The main register set is used to store data during the execution of the main program;

[0011] The shadow register set is used to store data when the interrupt server program is running.

[0012] The main register group includes at least one main register;

[0013] The shadow register group includes at least one shadow register;

[0014] The number of shadow register groups is the same as the number of main register groups, and their lengths are equal.

[0015] The interrupt controller is configured to, upon receiving the interrupt request signal, not execute the PUSH memory instruction to save the context of the main program, and not execute the POP memory instruction to restore the context of the main program.

[0016] The interrupt controller is further configured to: upon receiving the interrupt request signal, save the main program's program status PS / PSW to the stack, read the interrupt vector, and obtain the entry address of the interrupt service routine; and after the interrupt service routine is executed, restore the main program's PC / PSW from the stack, return from the interrupt, and execute the main program.

[0017] According to a second aspect, a method for implementing interrupt response in a processor system based on embodiments of the present invention is provided, the method comprising:

[0018] Execute the main program and use the main register set to store the data generated during the main program's execution;

[0019] The interrupt controller receives an interrupt request signal from an external source, which requests the execution of an interrupt service routine.

[0020] The interrupt controller sets the state of the control register to the first state value;

[0021] When the multiplexer reads the status value of the control register as the first status value, the multiplexer connects the shadow register group and the arithmetic unit;

[0022] The execution of the main program is paused, the interrupt service routine is executed, and the data during the execution of the interrupt service routine is stored using the shadow register set;

[0023] After the interrupt service routine has finished executing, the interrupt controller sets the state of the control register to the second state value;

[0024] When the multiplexer reads the status value of the control register as the second status value, the multiplexer connects the main register group and the arithmetic unit;

[0025] Continue executing the main program and use the main register set to store the data generated during the main program's execution.

[0026] The main register group includes at least one main register;

[0027] The shadow register group includes at least one shadow register;

[0028] The number of shadow register groups is the same as the number of main register groups, and their lengths are equal.

[0029] After the interrupt controller receives the interrupt request signal and before the interrupt service routine is executed, the method further includes: saving the main program's program state PS / program state word PSW to the stack; reading the interrupt vector and obtaining the entry address of the interrupt service routine;

[0030] After the interrupt service routine has completed execution and before the main program continues execution, the method further includes:

[0031] Restore the main program's PC / PSW from the stack and return from the interrupt.

[0032] The method further includes: the interrupt controller uses one clock cycle to switch the state value of the control register from the second state value of the corresponding main program to the first state value of the corresponding interrupt service routine.

[0033] The interrupt controller is configured to, upon receiving the interrupt request signal, not execute the PUSH memory instruction to save the context of the main program, and not execute the POP memory instruction to restore the context of the main program.

[0034] According to a third aspect, a computing device is provided, including a memory and a processor, wherein the memory stores executable code, and the processor executes the executable code to implement the method described in any embodiment of the present invention.

[0035] Therefore, the processor system and interrupt response method proposed in the embodiments of the present invention have at least the following advantages:

[0036] 1. Extremely low interrupt latency: By automatically switching registers in hardware, the memory access overhead caused by executing content instructions, i.e. saving and restoring a large number of registers in software, is eliminated in the existing technology. The context switching time is shortened from tens of clock cycles (generally more than 20 clock cycles) to 1-2 clock cycles.

[0037] 2. Simplified software design: Interrupt Service Routine (ISR) no longer needs to include cumbersome context saving and restoring code, making the program simpler, smaller, and more efficient in development;

[0038] 3. Deterministic response: The interrupt response time is deterministic and extremely short, unaffected by the number of registers used by the main program, making it very suitable for the requirements of hard real-time systems;

[0039] 4. High hardware efficiency: Compared with complex technologies such as register windows, the embodiments of the present invention are simple to implement, have controllable hardware overhead, and are easy to integrate into existing processor designs. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the processor system in one embodiment of the present invention.

[0042] Figure 2 This is a flowchart of an interrupt response method in one embodiment of the present invention.

[0043] Figure 3 This is a comparative schematic diagram of an interrupt response method according to an embodiment of the present invention.

[0044] Figure 4 This is a schematic diagram of a processor system architecture in one embodiment of the present invention. Detailed Implementation

[0045] The solution provided by the present invention will now be described with reference to the accompanying drawings.

[0046] First, it should be noted that the terminology used in the embodiments of this invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” used in the embodiments of this invention and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0047] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0048] One embodiment of the present invention provides a processor system, see [link to relevant documentation]. Figure 1 The processor system includes: an interrupt controller 101, a control register 102, a multiplexer 103, an arithmetic unit 104, a main register group 105, and a shadow register group 106.

[0049] Among them, the main register group 105 and the shadow register group 106 correspond one-to-one; one side of the multiplexer can be connected to the main register group or the shadow register group, and the other side is connected to the arithmetic unit;

[0050] Interrupt controller 101 is used to set the state of control register 102, receive an interrupt request signal sent from the outside to request the execution of an interrupt service routine, set the state of control register 102 to a first state value when the interrupt request signal is received, and set the state of control register 102 to a second state value after the interrupt service routine is completed.

[0051] Multiplexer 103 is used to read the status value of control register 102. When the read status value of control register 102 is the first status value, multiplexer 103 connects shadow register group 106 and arithmetic unit 104. When the read status value of control register 102 is the second status value, multiplexer 103 connects main register group 105 and arithmetic unit 104.

[0052] Main register group 105 is used to store data during the execution of the main program;

[0053] Shadow register group 106 is used to store data when the interrupt server program is running.

[0054] In existing technologies, both saving and restoring the context during interrupt response require executing multiple memory access instructions. For example, saving the context requires executing a PUSH instruction for each register saved. Since processors typically use dozens of registers, the time required to save the register set depends on the number of general-purpose registers and the number of registers pushed onto the stack. Saving the context for general-purpose registers generally takes tens of clock cycles (typically more than 20 clock cycles), making it a time-consuming operation in the interrupt response process and impacting interrupt response speed. Similarly, restoring the context involves overwriting the saved context content from the stack into the general-purpose register set using a POP instruction, which also takes tens of clock cycles (typically more than 20 clock cycles), making it a time-consuming operation for interrupt return.

[0055] Compared with the prior art, the processor system proposed in this embodiment of the invention has at least the following advantages:

[0056] 1. This invention uses a shadow register approach, eliminating the need for stack operations on the general-purpose register set. It directly switches the working register set from the main register set to the shadow register set, and the interrupt service routine executes directly on the shadow register set. Since this shadow register set is not used by the main program, the interrupt control program does not need to execute time-consuming PUSH instructions to save the context of the main task, thus it can immediately start processing interrupt events. The entire switching process is executed by hardware, with the multiplexer switching paths, without the need for software intervention. It can usually be completed in just one clock cycle, saving tens of clock cycles (generally more than 20 clock cycles) compared to the traditional method, effectively improving the interrupt response rate and achieving extremely low interrupt latency.

[0057] 2. In this embodiment of the invention, the context can be restored by switching registers. When returning from an interrupt, the multiplexer is controlled by the status value of the control register to switch the current working register from the shadow register group to the main register group. Since the main register group still contains the data / content of the main program before the interrupt, the purpose of switching the context can be achieved without additional operations. This operation is performed by hardware and does not require software participation. It can be completed in just one clock cycle. Compared with the prior art, it saves dozens of clock cycles (generally more than 20 clock cycles), effectively improves the interrupt return rate, and achieves extremely low interrupt latency.

[0058] 3. Simplified software design: Interrupt Service Routine (ISR) no longer needs to include cumbersome context saving and restoring code, making the program simpler, smaller in size, and more efficient in development;

[0059] 4. Deterministic response: The interrupt response time is deterministic and extremely short, unaffected by the number of registers used by the main program, making it very suitable for the requirements of hard real-time systems;

[0060] 5. High hardware efficiency: Compared with complex technologies such as register windows, the embodiments of the present invention are simple to implement, have controllable hardware overhead, and are easy to integrate into existing processor designs.

[0061] In one embodiment of the present invention, the main register group 105 includes at least one main register; the shadow register group 106 includes at least one shadow register; the shadow register group and the main register group include the same number of registers and have the same length. For example, 10 main registers form the main register group, and 10 shadow registers form the shadow register group.

[0062] As mentioned above, in one embodiment of the present invention, during the interrupt response process, the interrupt response is achieved by switching the main register group 105 to the shadow register group 106. The entire switching process is executed by hardware, and the multiplexer can switch paths without software intervention. Therefore, the interrupt controller 101 is configured to: after receiving the interrupt request signal, not execute the PUSH memory instruction to save the context of the main program, and not execute the POP memory instruction to restore the context of the main program.

[0063] In one embodiment of the present invention, the interrupt controller 101 is further configured to: upon receiving the interrupt request signal, save the program status PS / program status word PSW of the main program to the stack, read the interrupt vector, and obtain the entry address of the interrupt service routine; and after the interrupt service routine is executed, restore the PC / PSW of the main program from the stack, return from the interrupt, and execute the main program.

[0064] One embodiment of the present invention also proposes a method for implementing interrupt response, which is implemented based on the processor system of the present invention. See also Figure 1 , Figure 2 The interrupt response method includes:

[0065] Step 201: Execute the main program and use the main register set to store the data generated during the main program's execution;

[0066] Step 203: The interrupt controller receives an interrupt request signal from an external source, requesting the execution of an interrupt service routine;

[0067] Step 205: The interrupt controller sets the state of the control register to the first state value, such as 01;

[0068] Step 207: When the multiplexer reads the status value of the control register as the first status value, the multiplexer connects the shadow register group and the arithmetic unit;

[0069] Step 209: Pause the execution of the main program, execute the interrupt service routine, and use the shadow register set to store the data generated during the execution of the interrupt service routine;

[0070] Step 211: After the interrupt service routine has finished executing, the interrupt controller sets the status of the control register to the second status value, such as 00;

[0071] Step 213: When the multiplexer reads the status value of the control register as the second status value, the multiplexer connects the main register group and the arithmetic unit;

[0072] Step 215: Continue executing the main program and use the main register set to store the data generated during the main program's execution.

[0073] In one embodiment of the method of the present invention, after the interrupt controller receives the interrupt request signal in step 203 and before executing the interrupt service routine in step 209, the method further includes: saving the program status (PS) / program status word (PSW) of the main program to the stack; reading the interrupt vector and obtaining the entry address of the interrupt service routine;

[0074] After the interrupt service routine in step 211 has completed execution, and before the main program continues execution in step 215, the method further includes:

[0075] Restore the main program's PC / PSW from the stack and return from the interrupt.

[0076] In the embodiments of the present invention, PS and PSW are saved to the stack. The core purpose is to temporarily store the key state information of the main program running on the stack (a "last-in, first-out" storage area). The purpose is to restore the program state before the interruption after the interruption is completed, so that the original program can continue to execute normally.

[0077] PS is a register that records the current kernel state of the program. Its definition varies slightly across different processor architectures, but its core function is to store key markers directly related to program execution, such as:

[0078] • The register group number currently being used by the program;

[0079] • Partial information from the program counter (PC) (which records the address of the next instruction to be executed).

[0080] Some processors use PS to record the privilege level of a program (such as user mode or system mode).

[0081] The PSW (Power Switch) is responsible for centrally storing the CPU's operating state and calculation result markers. This is critical information that must be protected during interrupts, and typically includes:

[0082] • Operation flags: such as carry flag (C), zero flag (Z), overflow flag (V), etc. (e.g., whether there is a carry during addition, or whether the result of the operation is 0).

[0083] • Interrupt control bits: such as the interrupt enable flag (IE) (which determines whether the CPU can respond to other interrupts).

[0084] • Status flags: such as program running mode (e.g., sleep mode, normal mode) and error flags (e.g., parity error).

[0085] Simply put, both PS and PSW are "state recorders" of the CPU. When an interrupt occurs, they are saved to the stack, just like when a movie is paused, the playback progress and screen state are recorded, and the state can be accurately restored to the state when it was paused.

[0086] In one embodiment of the method of the present invention, it further includes: the interrupt controller uses one clock cycle to switch the state value of the control register from the second state value of the corresponding main program to the first state value of the corresponding interrupt service routine.

[0087] In one embodiment of the method of the present invention, it further includes: the interrupt controller uses one clock cycle to switch the state value of the control register from the first state value of the corresponding interrupt service routine to the second state value of the corresponding main program.

[0088] Figure 3 This is a comparative schematic diagram of an interrupt response method according to an embodiment of the present invention. See also... Figure 3 The process of the interrupt response method in another embodiment of the present invention can be obtained. See also Figure 3 This invention employs a shadow register approach, eliminating the need for stack operations on the general-purpose register set. It directly switches the working register set from the main register set to the shadow register set, and the interrupt service routine executes directly on the shadow register set. Since this shadow register set is not used by the main program, the interrupt control program does not need to execute time-consuming PUSH instructions to save the main task's context, thus allowing it to immediately begin handling interrupt events. The entire switching process is executed by hardware, with the multiplexer switching paths; no software intervention is required. It typically takes only one clock cycle to complete, saving tens of clock cycles (generally more than 20 clock cycles) compared to traditional methods, effectively improving interrupt response speed and achieving extremely low interrupt latency. See also... Figure 3In this embodiment of the invention, the context can be restored by switching registers. When returning from an interrupt, the multiplexer is controlled by the status value of the control register to switch the current working register from the shadow register group to the main register group. Since the main register group still contains the data / content of the main program before the interrupt, the purpose of switching the context can be achieved without additional operations. This operation is performed by hardware and does not require software participation. It can be completed in just one clock cycle. Compared with the prior art, it saves dozens of clock cycles (generally more than 20 clock cycles), effectively improves the interrupt return rate, and achieves extremely low interrupt latency.

[0089] Figure 4 This is a schematic diagram of a processor system architecture according to one embodiment of the present invention. See also... Figure 4 In one embodiment of the present invention, the processor system architecture includes the processor system proposed in any embodiment of the present invention and the system memory 401. The system memory is memory. The processor system of the present invention is connected to the system memory 401 through a data / address bus.

[0090] One embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to perform the method in any of the embodiments of the specification.

[0091] One embodiment of the present invention provides a computing device, including a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, it implements the method of any embodiment in the specification.

[0092] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the apparatus of the embodiments of the present invention. In other embodiments of the specification, the above-described apparatus may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0093] The various embodiments in this invention are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0094] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using hardware, software, widgets, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium.

[0095] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A processor system, characterized in that, The processor system includes: an interrupt controller, a control register, a multiplexer, an arithmetic unit, a main register set, and a shadow register set; The main register group and the shadow register group correspond one-to-one; one side of the multiplexer can be connected to either the main register group or the shadow register group, and the other side is connected to the arithmetic unit; The interrupt controller is used to set the state of the control register, receive an interrupt request signal from the outside to request the execution of an interrupt service routine, set the state of the control register to a first state value when the interrupt request signal is received, and set the state of the control register to a second state value after the interrupt service routine is completed. The multiplexer is used to read the status value of the control register. When the read status value of the control register is the first status value, the multiplexer connects the shadow register group and the arithmetic unit. When the read status value of the control register is the second status value, the multiplexer connects the main register group and the arithmetic unit. The main register set is used to store data during the execution of the main program; The shadow register set is used to store data when the interrupt server program is running.

2. The processor system according to claim 1, characterized in that, The main register group includes at least one main register; The shadow register group includes at least one shadow register; The shadow register group has the same number of registers and the same length as the main register group.

3. The processor system according to claim 1, characterized in that, The interrupt controller is configured to, upon receiving the interrupt request signal, not execute the PUSH memory instruction to save the context of the main program, and not execute the POP memory instruction to restore the context of the main program.

4. The processor system according to claim 1, characterized in that, The interrupt controller is further configured to: upon receiving the interrupt request signal, save the main program's program state PS / program state word PSW to the stack, read the interrupt vector, and obtain the entry address of the interrupt service routine; After the interrupt service routine is completed, the main program's PC / PSW is restored from the stack, the interrupt returns, and the main program is executed.

5. A method for implementing interrupt response based on the processor system according to any one of claims 1 to 4, characterized in that, The method includes: Execute the main program and use the main register set to store the data generated during the main program's execution; The interrupt controller receives an interrupt request signal from an external source, which requests the execution of an interrupt service routine. The interrupt controller sets the state of the control register to the first state value; When the multiplexer reads the status value of the control register as the first status value, the multiplexer connects the shadow register group and the arithmetic unit; The execution of the main program is paused, the interrupt service routine is executed, and the data during the execution of the interrupt service routine is stored using the shadow register set; After the interrupt service routine has finished executing, the interrupt controller sets the state of the control register to the second state value; When the multiplexer reads the status value of the control register as the second status value, the multiplexer connects the main register group and the arithmetic unit; Continue executing the main program and use the main register set to store the data generated during the main program's execution.

6. The method according to claim 5, characterized in that, The main register group includes at least one main register; The shadow register group includes at least one shadow register; The shadow register group has the same number of registers and the same length as the main register group.

7. The method according to claim 5, characterized in that, After the interrupt controller receives the interrupt request signal and before the interrupt service routine is executed, the method further includes: saving the main program's program state PS / program state word PSW to the stack; reading the interrupt vector and obtaining the entry address of the interrupt service routine; After the interrupt service routine has completed execution and before the main program continues execution, the method further includes: Restore the main program's PC / PSW from the stack and return from the interrupt.

8. The method according to claim 5, characterized in that, The method further includes: the interrupt controller uses one clock cycle to switch the state value of the control register from the second state value of the corresponding main program to the first state value of the corresponding interrupt service routine.

9. The method according to claim 5, characterized in that, The interrupt controller is configured to, upon receiving the interrupt request signal, not execute the PUSH memory instruction to save the context of the main program, and not execute the POP memory instruction to restore the context of the main program.

10. A computing device comprising a memory and a processor, wherein the memory stores executable code, and the processor, when executing the executable code, implements the method of any one of claims 1-4.

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