EEPROM data read-write method and device based on real-time industrial Ethernet and medium

Abstract

The invention provides an EEPROM (Electrically Erasable Programmable Read-Only Memory) data read-write method and device based on a real-time industrial Ethernet and a medium. The method comprises the following steps: setting an initial offset and an access length of EEPROM access on a target slave station according to EEPROM capacity parameters, and establishing a paging transaction; when the paging transaction is of a reading type, sequentially triggering EEPROM control registers of the target slave station, reading EEPROM data to a buffer area of the master station according to pages from the initial offset, and executing cyclic redundancy check on each page of read data; when the paging transaction is of a write-in type, reading a to-be-written data file into a buffer area of the master station, writing the to-be-written data file into an EEPROM (Electrically Erasable Programmable Read-Only Memory) of a target slave station according to a page sequence from initial offset, and after writing of each page is completed, reading back data of the page and executing cyclic redundancy check; and when all page data of the paging transaction of the reading type or the writing type passes cyclic redundancy check, outputting a transaction completion state to the soft programmable logic controller. According to the method and the device, the technical effects of safely, efficiently and accurately reading and writing the EEPROM on line in batches and ensuring the data consistency can be achieved.

Description

Technical Field

[0001] The present application relates to the field of industrial automation technology, and in particular to a method, device and medium for reading and writing EEPROM data based on real-time industrial Ethernet. Background Art

[0002] In the field of industrial automation, various sensors, actuators, servo drives, and embedded controllers typically use electrically erasable programmable read-only memory (EEPROM) to store manufacturer parameters, device identification, firmware version, and user configuration data. After the device is powered on or reset, the EtherCAT slave controller (ESC) automatically loads the preset register configuration data in the EEPROM into internal registers, placing the slave in its intended operating mode. As automated equipment continues to evolve toward high-speed, high-precision, and multi-axis collaboration, the frequency of firmware upgrades and parameter modifications required for field equipment has increased significantly, placing higher real-time and reliability requirements on online EEPROM read and write operations during operation.

[0003] In the prior art, the following methods are mainly used to read and write the EEPROM of the EtherCAT slave: Use the dedicated burner or host computer tool provided by the device manufacturer to 2 C or UART interface to erase and write EEPROM in offline state; Relying on general EtherCAT configuration software, data transmission is completed through commands such as FoE (File over EtherCAT), CoE (SDO upload / download), or EEPROM Tool within the network idle window; Embed a simple EEPROM script in the soft PLC or edge gateway, manually specify the logical address of the target slave, read and write by page, and save the data to a local file.

[0004] The above-mentioned existing technologies still have the following problems: the offline burning method requires manual disconnection of the network or disassembly of the equipment, which affects the production rhythm and is prone to misconnection; the general configuration tool relies on manual selection of binding network ports. If the ENI (Engineering Network Information) file is inconsistent with the actual topology, it is easy to cause logical address mismatch or erroneous writing of other slaves; the script method lacks transaction control and data verification mechanisms, and cannot guarantee data consistency in the event of unexpected power failure or link jitter during the continuous writing of multiple pages; traditional tools generally forward frames at the byte level and handshake node by node, which is inefficient when processing EEPROMs with a capacity of more than 1 Mbit and cannot meet microsecond real-time communication scenarios; there is a lack of unified exception rollback and verification failure recovery strategies. Manual re-burning is often required after writing errors or verification inconsistencies, which leads to high maintenance costs. Summary of the Invention

[0005] In view of this, the embodiments of the present application provide an EEPROM data reading and writing method, device and medium based on real-time industrial Ethernet to solve the problems existing in the prior art such as offline burning shutdown, logical address mismatch and erroneous writing, lack of transactions and bidirectional CRC checking resulting in difficulty in ensuring data consistency, low reading and writing efficiency and insufficient real-time performance.

[0006] In a first aspect of an embodiment of the present application, a method for reading and writing EEPROM data based on real-time industrial Ethernet is provided, comprising: loading a real-time industrial Ethernet communication dynamic library, establishing a real-time industrial Ethernet master station according to a preset media access control address; during the startup process of the real-time industrial Ethernet master station, scanning the real-time industrial Ethernet, obtaining slave link topology information, assigning a logical address to each detected slave station, and generating a slave link information table; matching the slave station information in the engineering network information file with the slave link information table, and recording the physical address and EEPROM capacity parameters of the corresponding target slave station in an internal cache when the match is successful; and performing a read and write operation on the target slave station according to the EEPROM capacity parameters. The starting offset and access length of the EEPROM access are set to establish a paging transaction. When the paging transaction is of read type, the EEPROM control register of the target slave station is triggered in sequence, and the EEPROM data is read into the master station buffer page by page starting from the starting offset, and a cyclic redundancy check is performed on each page of data read. When the paging transaction is of write type, the data file to be written is read into the master station buffer, and written to the EEPROM of the target slave station in page order starting from the starting offset. After each page is written, the page data is read back and a cyclic redundancy check is performed. When all page data of the read type or write type paging transaction pass the cyclic redundancy check, the transaction completion status is output to the soft programmable logic controller.

[0007] According to a second aspect of the embodiment of the present application, an EEPROM data reading and writing device based on real-time industrial Ethernet is provided, comprising: a loading module for loading a real-time industrial Ethernet communication dynamic library and establishing a real-time industrial Ethernet master station according to a preset media access control address; a scanning module for scanning the real-time industrial Ethernet during the startup of the real-time industrial Ethernet master station, obtaining slave link topology information, assigning a logical address to each detected slave station, and generating a slave link information table; a matching module for matching the slave information in the engineering network information file with the slave link information table, and recording the physical address and EEPROM capacity parameters of the corresponding target slave station in the internal cache when the match is successful; a setting module for setting the EEPROM capacity parameters on the target slave station according to the EEPROM capacity parameters on the target slave station. The M capacity parameter sets the starting offset and access length of the EEPROM access to establish a paging transaction; the read module is used to trigger the EEPROM control register of the target slave station in sequence when the paging transaction is of the read type, read the EEPROM data into the master station buffer page by page starting from the starting offset, and perform a cyclic redundancy check on each page of data read; the write module is used to read the data file to be written into the master station buffer when the paging transaction is of the write type, write the data to the EEPROM of the target slave station in page order starting from the starting offset, read back the page data after each page is written and perform a cyclic redundancy check; the output module is used to output the transaction completion status to the soft programmable logic controller when all page data of the read type or write type paging transaction pass the cyclic redundancy check.

[0008] According to a third aspect of an embodiment of the present application, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the steps of the above method are implemented when the processor executes the computer program.

[0009] According to a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided, which stores a computer program. When the computer program is executed by a processor, the steps of the above method are implemented.

[0010] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: By loading the real-time industrial Ethernet communication dynamic library, a real-time industrial Ethernet master station is established according to the preset media access control address; during the startup process of the real-time industrial Ethernet master station, the real-time industrial Ethernet is scanned to obtain the slave link topology information, a logical address is assigned to each detected slave station, and a slave link information table is generated; the slave information in the project network information file is matched with the slave link information table, and when the match is successful, the physical address and EEPROM capacity parameters of the corresponding target slave station are recorded in the internal cache; the starting offset and access length of the EEPROM access are set on the target slave station according to the EEPROM capacity parameters degree, establish a paging transaction; when the paging transaction is of read type, trigger the EEPROM control register of the target slave station in sequence, read the EEPROM data from the starting offset to the master station buffer page by page, and perform a cyclic redundancy check on each page of data read; when the paging transaction is of write type, read the data file to be written into the master station buffer, write the EEPROM of the target slave station in page order from the starting offset, read back the page data after each page is written and perform a cyclic redundancy check; when all page data of the read type or write type paging transaction pass the cyclic redundancy check, output the transaction completion status to the soft programmable logic controller. This application can achieve the technical effect of online safe, efficient and accurate batch reading and writing of EEPROM and ensuring data consistency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 This is a schematic diagram of the framework of the Sinsegye Ethercat bus communication software system provided in an embodiment of the present application; Figure 2 This is a schematic diagram of the overall process of reading and writing EEPROM data provided by the embodiment of the present application; Figure 3 1 is a flow chart of a method for reading and writing EEPROM data based on real-time industrial Ethernet provided in an embodiment of the present application; Figure 4 Schematic diagram of the structure of an EEPROM data reading and writing device based on real-time industrial Ethernet provided in an embodiment of the present application; Figure 5 It is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0014] The primary purpose of this application is to provide a high-efficiency EEPROM (Electrically Erasable Programmable Read-Only Memory) read / write solution based on the EtherCAT (Ethernet for Control Automation Technology) protocol. This solution enables EEPROM storage media operations, including data read and write, between devices and the master in an EtherCAT network. To meet the high real-time and high-efficiency requirements of industrial automation environments, the software design fully leverages the advantages of the EtherCAT protocol.

[0015] EtherCAT is a high-performance, real-time Ethernet communication protocol designed for real-time control and data exchange in industrial automation systems. EtherCAT uses an efficient frame-based transmission mechanism to ensure fast and accurate data flow between network devices, minimizing communication latency and bandwidth usage. It offers the following key advantages: Efficient data transmission: EtherCAT adopts a frame-based transmission mechanism. Data frames are broadcast through each device node, and only relevant data is read and modified. This avoids the high latency of traditional Ethernet node-by-node forwarding and greatly improves data transmission efficiency.

[0016] Real-time performance: The EtherCAT protocol can provide low-latency data exchange in microseconds, meeting the strict real-time requirements of industrial automation and control systems and ensuring high-precision control.

[0017] Scalability and flexibility: EtherCAT supports multiple network topologies (such as star, ring, and line), can flexibly connect a large number of devices, and is suitable for industrial control networks of various sizes.

[0018] Combining these advantages of the EtherCAT protocol, this software achieves the following goals: Efficient EEPROM read and write operations: Leveraging the data transmission capabilities of the EtherCAT protocol, EEPROM data can be read and written in real-time environments with data transmission latency as low as microseconds.

[0019] Data integrity and security: When performing EEPROM reading and writing, precise control mechanisms ensure data accuracy, avoid data loss or corruption, and improve system stability and reliability.

[0020] Multi-device support and compatibility: This software supports compatibility with various EtherCAT-based devices, can effectively communicate with industrial equipment such as sensors, actuators, PLCs, and supports customized configurations for different hardware platforms.

[0021] Optimized device management and maintenance: The software encapsulates the underlying details of the EtherCAT protocol, providing a high-level interface that simplifies user operations and makes device configuration, monitoring, and troubleshooting more convenient.

[0022] Modularity and scalability: The modular design of this software supports later functional expansion and can easily integrate other protocols or devices as needed to ensure the scalability of the system.

[0023] Support for industrial automation applications: This software is suitable for a variety of industrial automation environments and is widely used in embedded systems, intelligent manufacturing, power management, robotic control and other fields, especially in scenarios where efficient and reliable operation of EEPROM storage in EtherCAT networks is required.

[0024] With this solution, users can efficiently manage and operate EEPROM storage devices in the EtherCAT network, improving the data transmission efficiency and real-time control capabilities of industrial automation systems.

[0025] The information stored in the EEPROM is written by the manufacturer and describes the slave device. The EEPROM capacity ranges from 1Kbit to 4Mbit, depending on the ESC specifications. Users can read and write this information through the EEPROM control registers in the ESC. Additionally, upon powering on or resetting the device, the ESC automatically reads data from the ESC register configuration area in the EEPROM and writes it to the corresponding registers to complete the ESC configuration.

[0026] Sinsegye Ethercat's EEPROM file reading and writing software ensures accurate reading and writing of EEPROM data in applications requiring high reliability and data security, preventing data loss, corruption, or inconsistency, and meeting industrial-grade data protection and security requirements.

[0027] Compatible with multiple platforms, the software can perform EEPROM data configuration and management tasks between the master and slave devices in an EtherCAT network if the current slave configuration is corrupted. For example, it can retrieve files generated by Twincat to configure the device's operating mode, store device parameters, and update device firmware.

[0028] Sinsegye Ethercat bus communication software system architecture Figure 1 As shown, Figure 1 This is a schematic diagram of the framework of the Sinsegye Ethercat bus communication software system provided in the embodiment of the present application, which consists of Figure 1 It can be seen that the Sinsegye Ethercat bus communication software is dynamically loaded into the soft PLC, and then the Ethercat software establishes communication through MAC, and then performs file transfer.

[0029] The following combination Figure 1 The framework shown in the figure describes the overall process of using the above software to perform EEPROM data reading and writing. Figure 2 This is a schematic diagram of the overall process of reading and writing EEPROM data provided by the embodiment of the present application, such as Figure 2 As shown, the overall process of EEPROM data reading and writing of this application includes the following steps: exist Figure 1 In the system architecture shown, the Codesys PLC Runtime Environment (RTE) establishes a data channel with the EtherCAT software module via a dynamically loaded real-time Industrial Ethernet communication library. The EtherCAT software module then connects to the I / O modules, various EtherCAT slaves, motion controllers, and industrial gateways via physical network ports. Based on this architecture, the EEPROM data read and write process proceeds through the following stages.

[0030] 1. Master station initialization (corresponding to Figure 2 "Add Ethercat → Start Ethercat") After the soft PLC boots up, it first parses the configuration file, mounts the communication dynamic library according to the preset MAC address, and establishes a real-time Industrial Ethernet master. After entering the INIT state, the master sends auto-increment detection frames, discovering slaves along the link and recording their physical order. Once detection is complete and the internal FMMU and SyncManager mapping is established, the master switches to the operational state following the PREOP → SAFEOP → OP sequence. It then reads the initial parameters from the loaded ENI file and distributes them to the corresponding slave registers, achieving network-level synchronization configuration.

[0031] 2. Slave station information storage and communication confirmation (corresponding to Figure 2 "Scan and detect link slaves → download configuration files → confirm that the slaves can communicate → record the slave addresses") The master station performs a cyclic scan of the link in the OP state, reads the manufacturer identification, product number, serial number and alias information of each slave station through the APRD read instruction, and generates a slave link information table; at the same time, it assigns a unique logical address to each slave station and writes it into the LRAM. The master station then sends a working status detection frame to each slave station, reads the ALStatus bit to determine the communication quality, and proceeds to the next step only when the working status is OP and there is no error flag. For slave stations in normal status, the master station writes its physical address, logical address and device type into the internal cache as the target index for subsequent EEPROM access; if a slave station fails to communicate, it goes along Figure 2 The right branch returns to the "Scan Detect Link Slaves" node to try again.

[0032] 3. Configuration file verification (corresponding to Figure 2 "Download the configuration file → Check if the configuration file is correct") After caching is complete, the master parses the ENI or XML-formatted engineering network information file and compares each slave's information declared in the file with the link information table. If the comparison results are identical, the PDO mapping, synchronization period, and other parameters in the file are downloaded to the target slave and the CRC of the received receipt is read. If the CRC matches, the configuration file is considered correct, and the process enters the EEPROM transaction phase. If the CRC is inconsistent or the comparison fails, the "Error" node on the left is triggered, the exception is recorded, and the current operation is terminated.

[0033] 4. Confirmation of EEPROM address and parameters (corresponding to Figure 2 "Eeprom address and parameter confirmation") For the target slave station that has been confirmed to be communicable, the master station reads its EEPROMStationAlias, EEPROMSize and other register fields to obtain the EEPROM capacity parameters; the operator enters the starting offset and access length on the host computer interface according to specific needs, and the system generates a paging descriptor based on the capacity parameters and writes it into the EEPROM control register of the target slave station to establish a paging transaction session.

[0034] 5. Specific read and write operations (corresponding to Figure 2 "read and write") After the paging transaction is initialized, if the read type is selected, the master triggers the EEPROM read command page by page, moves the data to the master buffer, and performs a bidirectional CRC check. Data that passes the check is immediately written to the external backup file. If the write type is selected, the master first de-pages the file to be written into the cache, then writes it page by page to the EEPROM and reads back each page for verification. If a check fails, the transaction is terminated and the data is rolled back to the pre-write backup state.

[0035] 6. Completion and Result Reporting When all page data passes the CRC check, the master station writes the transaction completion status and result code to the upper-level interface of the soft PLC. The soft PLC then triggers subsequent process or maintenance logic based on this information. If an exception occurs at any stage, the system outputs detailed error information through the "Error Report" node on the left and safely terminates the process, avoiding any impact on field equipment.

[0036] Through the above steps, this application implements a complete link from master station establishment, slave station authentication, configuration consistency verification to paged transaction-level EEPROM reading and writing inside the soft PLC, which not only ensures on-site real-time performance, but also enhances data integrity and operation and maintenance security.

[0037] The contents of the technical solution of this application are described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] Figure 3 1 is a flow chart of a method for reading and writing EEPROM data based on real-time industrial Ethernet provided in an embodiment of the present application. Figure 3 As shown, the EEPROM data reading and writing method based on real-time industrial Ethernet may specifically include: S301, loading the real-time industrial Ethernet communication dynamic library and establishing a real-time industrial Ethernet master station according to a preset media access control address; S302, during the startup of the real-time industrial Ethernet master station, scanning the real-time industrial Ethernet, obtaining slave link topology information, assigning a logical address to each detected slave station, and generating a slave link information table; S303, matching the slave station information in the project network information file with the slave station link information table, and recording the physical address and EEPROM capacity parameters of the corresponding target slave station in the internal cache when the match is successful; S304, setting the starting offset and access length of the EEPROM access according to the EEPROM capacity parameter on the target slave station, and establishing a paging transaction; S305, when the paging transaction is of read type, triggering the EEPROM control register of the target slave station in sequence, reading EEPROM data page by page from the starting offset to the master station buffer, and performing a cyclic redundancy check on each page of data read; S306, when the paging transaction is of write type, the data file to be written is read into the master station buffer, and written to the EEPROM of the target slave station in page order starting from the starting offset. After each page is written, the page data is read back and a cyclic redundancy check is performed; S307: After all page data of the read or write paging transaction pass the cyclic redundancy check, the transaction completion status is output to the soft programmable logic controller.

[0039] In some embodiments, loading a real-time industrial Ethernet communication dynamic library and establishing a real-time industrial Ethernet master station according to a preset media access control address includes: Mount the dynamic link library containing the real-time industrial Ethernet protocol stack to the soft programmable logic controller operating environment through the configuration file; Parse the target network port media access control address in the configuration file and obtain the actual media access control address of the device where the soft programmable logic controller is located; Compare the target network port media access control address with the actual media access control address. If the comparison is consistent, enable the original data frame transceiver channel on the corresponding network port and start the real-time industrial Ethernet master station state machine. If the comparison is inconsistent, output the binding exception information and terminate the master station establishment process.

[0040] Specifically, on an industrial control computer equipped with dual Gigabit Ethernet interfaces, the operating system enters the soft programmable logic controller runtime environment after booting. Operations and maintenance personnel place a pre-generated configuration file, "fieldbus.cfg," in a fixed directory. This file specifies the dynamic library path, target network port name, and target media access control address using key-value pairs. For example, the dynamic library path is specified as " / usr / lib / librte-ec.so," the target network port name is specified as "eth1," and the corresponding target media access control address is written as the hexadecimal string "00-0A-35-1C-2B-7E."

[0041] The system first performs configuration parsing: The parsing thread reads the configuration file line by line, storing the dynamic library path, network port name, and target media access control address into an internal parameter structure. It then calls the file system interface to verify the existence of the dynamic library and its executable load permissions. Once verified, the soft PLC, at runtime, uses the operating system's dynamic linker function to map "librte-ec.so" into its process address space and triggers the library entry function to initialize the protocol stack. The protocol stack internally establishes a message transceiver engine, a frame buffer ring queue, and a master state machine control block.

[0042] After the protocol stack completes its self-test, the initialization thread queries the operating system's network stack based on the configured network port name, obtains the physical interface descriptor named "eth1," and reads the actual media access control address from the kernel's network subsystem. The address read is "00-0A-35-1C-2B-7E." The system then performs a byte-level comparison of the actual media access control address with the target media access control address in the configuration file. The comparison results are identical, indicating that the current physical interface matches the configuration file.

[0043] After a match is found, the protocol stack issues a privileged call to the physical interface, opening the original frame transmission and reception channel. Simultaneously, the interface driver layer enables a no-copy ring buffer and adjusts interrupt aggregation parameters to ensure that single-frame latency meets real-time requirements. After completing the underlying resource allocation, the protocol stack instantiates the real-time Industrial Ethernet master state machine, sets its state to INIT, and registers a callback handle with the soft programmable logic controller for subsequent task scheduling threads. When the master state machine reaches the end of INIT, it issues a link detection frame and continues with slave discovery and logical address allocation.

[0044] Furthermore, if the actual media access control address is found to be inconsistent with the target media access control address in the configuration file during the comparison phase, the initialization thread immediately generates a binding exception message containing the detection timestamp, the target network port name, the expected address and the actual address, and writes it to the diagnostic log. The protocol stack then cancels the loaded dynamic library mapping, releases the occupied driver resources, and returns the error code "EC-MAC-MISMATCH" to the soft programmable logic controller, and the master station establishment process is terminated. This embodiment avoids the risk of field bus miswriting caused by incorrectly binding the real-time industrial Ethernet master station to an unexpected physical interface by checking the consistency of the media access control address.

[0045] In some embodiments, a real-time industrial Ethernet is scanned to obtain slave link topology information, a logical address is assigned to each detected slave, and a slave link information table is generated, including: After the real-time industrial Ethernet master enters the initialization state, it continuously sends auto-increment address detection frames to identify the physical address sequence of each slave station in the network; Write a unique logical address to each identified slave station and read the slave station's manufacturer identification, product number, serial number and alias information; The logical address and the corresponding physical address as well as the manufacturer identification, product number, serial number and alias information are recorded in the identification order to generate a slave link information table.

[0046] Specifically, after the master station completes initialization and enters the INIT state in the previous embodiment, the real-time Industrial Ethernet protocol stack initiates the slave station discovery thread. This thread first switches the master station state to "auto-increment addressing" mode and periodically sends auto-increment address detection frames on the bus with a fixed frame length of 64 bytes. The address field of the detection frame increments from 0, and each increment triggers the address response function unit of the next slave station.

[0047] In this example, the field network consists of four slave stations connected in series: an integrated I / O module, a servo drive, a temperature acquisition module, and an industrial gateway. When the detection frame address field is 0, the integrated I / O module at the head of the link responds first and returns the contents of the station register containing its physical address. The master station records the returned value, increments the detection frame address field to 1, and retransmits the message, sequentially identifying the physical addresses of the next three slave stations. Sequential acquisition of all physical addresses completes in approximately 250 µs.

[0048] The master then switches to "Write Logical Address" mode. In this mode, the master uses a counter to count the number of identified slaves and then writes logical addresses 0, 1, 2, and 3 to the four slaves in physical order, starting at 0. Logical address writing uses a two-byte write operation to registers 0x0120 to 0x0121. After each write, the master reads register 0x0130 to confirm that the logical address latch flag is set.

[0049] After writing the logical address, the master initiates a unicast read request to each slave, sequentially reading the manufacturer information object 0x1018 in the ESC configuration area and the alias field in the SII (Application Information) area. For the I / O module at logical address 0, the master first reads sub-indexes 01-03 of 0x1018 to obtain the manufacturer identifier value 0x000000AB, the product number 0x10020001, and the serial number 0x00000003. It then reads the AliasName field in the SII area to obtain the string "I / OA." Similarly, the manufacturer information and alias names of the servo drive, temperature acquisition module, and industrial gateway are sequentially obtained.

[0050] When all reading is completed, it is found that the thread generates the slave link information table in physical order. The table entry content includes the logical address, physical address, manufacturer identification, product number, serial number and alias. The first record generated in this embodiment is as follows: Logical address 0, physical address 0x0000, vendor identifier 0x000000AB, product number 0x10020001, serial number 0x00000003, alias "I / OA." This continues until the information for the industrial gateway at logical address 3 is recorded. This information table is written to the protocol stack shared memory area and timestamped with the "LINKMAP-TS" tag.

[0051] Finally, the discovery thread switches the master station state to the “topology determined” flag and sends an event notification to the soft programmable logic controller, indicating that the link information table is ready and can be used for subsequent configuration file verification and EEPROM transaction establishment.

[0052] This embodiment quickly identifies the physical order of slave stations through automatically incrementing address detection frames, achieving batch allocation of logical addresses without human intervention; at the same time, it instantly collects manufacturer information and aliases and generates a link information table, laying a data foundation for configuration consistency verification and accurate EEPROM target positioning, significantly reducing the risk of topology mismatch and miswrite, and improving system deployment efficiency and reliability.

[0053] In some embodiments, the slave station information in the engineering network information file is matched with the slave station link information table, and when the match is successful, the physical address and EEPROM capacity parameters of the corresponding target slave station are recorded in the internal cache, including: Parse the engineering network information file to extract the manufacturer identification, product number, serial number, alias, and expected physical location of each slave station; Traverse the slave link information table and read the corresponding slave's manufacturer identification, product number, serial number and alias information in logical address order; Compare the slave information in the project network information file with the information in the slave link information table one by one. If all the comparison results are consistent, the target slave is determined to be matched successfully. Read the EEPROM capacity parameters at the successfully matched target slave station and write them into the internal cache together with the physical address of the target slave station; For slaves with inconsistent comparison results, matching exception information is generated and output to the soft programmable logic controller.

[0054] Specifically, after the automatic discovery thread generates the link information table and writes it into the shared storage area, the configuration verification thread is scheduled for execution by the soft programmable logic controller. First, the system locates the configuration file directory and opens the engineering network information file "plant_line1.eni". This file uses XML syntax and contains four <device>The sub-nodes describe the I / O module, servo drive, temperature acquisition module and industrial gateway in turn. The configuration verification thread uses the built-in XML parser to traverse the nodes from top to bottom. <device>Extract the attributes VendorID, ProductCode, RevisionNo, AliasName and ExpectedPosition. <device>For example, the attribute values ​​of the node are 0x000000AB, 0x10020001, 0x00000003, I / OA, and 0. The parser writes all attribute values ​​into the project information list and keeps them consistent with the order in which the XML nodes appear.

[0055] After the file is parsed, the configuration verification thread reads the slave link information table generated in the previous embodiment from the shared storage area. The thread traverses the link information table in the order of logical addresses 0 → 3, and compares the read manufacturer identification, product number, serial number, and alias with the corresponding fields in the project information list. When all four fields are consistent and the link sequence matches the ExpectedPosition field, the match is considered successful and the match flag is set to 1. If any field is inconsistent or out of order, the match flag is immediately set to 0 and the reason for the discrepancy is recorded.

[0056] For the target slave whose match flag is 1, the thread uses the APRD instruction to read the Size field in its EEPROM control register 0x0502 and parse it to obtain the EEPROM capacity parameter. For example, the I / O module at logical address 0 returns a Size value of 0x0200, corresponding to a capacity of 512 x 16 bits. The thread then writes the target slave's physical address 0x0000 and the capacity parameter 512 x 16 bits into the internal buffer "EE_TARGETS." This cache uses a key-value format, with the physical address as the key and the capacity parameter and the current timestamp as the value, for subsequent paging transaction modules to call.

[0057] If the comparison process finds that the temperature acquisition module at logical address 2 is aliased as "T-Cold" but recorded as "T-Sensor" in the project file, the thread immediately generates a match exception message containing the inconsistent fields, expected values, actual values, and detection time. This exception information is sent to the soft programmable logic controller via the diagnostic interface and triggers the fault LED to flash. Based on the configuration policy, the system suspends subsequent EEPROM operations and waits for confirmation from maintenance personnel before reloading the revised project file or rescanning the link.

[0058] This embodiment verifies the consistency between the configuration file and the actual topology by comparing the project network information file with the field link information table item by item and writing the physical address and EEPROM capacity parameters only for slaves that fully match. This prevents miswrites caused by outdated project files or topology changes. Furthermore, real-time extraction and caching of capacity parameters provide precise boundaries for subsequent paging transactions, ensuring address legitimacy and data integrity during EEPROM read and write processes.

[0059] In some embodiments, setting the starting offset and access length of the EEPROM access on the target slave station according to the EEPROM capacity parameter to establish a paging transaction includes: Call the transaction configuration subroutine according to the EEPROM capacity parameter, calculate the number of bytes in a single page and the upper limit of the number of pages, and generate a paging descriptor including the starting offset, access length and the number of bytes in a single page; Write the paging descriptor through the EEPROM control register group of the target slave station and set the transaction type flag to start the paging access state machine; After the paging access state machine enters the ready state, it locks the EEPROM bus arbitration resource of the target slave station and establishes a buffer mapping corresponding to the paging descriptor on the master side to provide an index and readback verification benchmark for subsequent page reading and writing.

[0060] Specifically, after the previous example successfully writes the physical address and capacity parameters of the integrated I / O module at logical address 0 into the cache "EE_TARGETS," the paging transaction module is scheduled for execution. The cache record indicates that the EEPROM capacity of the target slave is 512 x 16 bits, or 1024 bytes. The operator selects "Backup Full EEPROM" on the host computer interface, and the system automatically sets the starting offset to 0 and the access length to 1024 bytes.

[0061] The transaction configuration subroutine first reads the capacity parameter 1024 bytes and calls the paging policy library to determine the number of bytes per page. Taking into account the maximum transmission unit and link delay supported by the target slave station, this embodiment sets the number of bytes per page to 128 bytes, so the upper limit of the number of pages is calculated to be 8. The subroutine then constructs a paging descriptor, the fields of which include: starting offset 0, access length 1024, number of bytes per page 128, total number of pages 8, current page index 0, and transaction type READ. The descriptor is encapsulated as a 16-byte structure and written to the EEPROM control register group of the target slave station according to the register map, where the offset register writes the starting address, the length register writes the access length, the page size register writes 128, and the control register writes the transaction type bit and the start bit.

[0062] After the write is complete, the master reads the status bit in the same control register to confirm that the page access state machine has switched from IDLE to PREPARE. The state machine internally freezes all other arbitration requests from the slave's EEPROM interface to ensure exclusive bus access during subsequent read and write operations. The master also allocates a 1024-byte ring buffer in the high-speed memory area, divided into eight slots based on the 128-byte page size. A one-to-one mapping is established between the buffer address and the page index in the page descriptor. After each subsequent page is read, the "VALID" flag is set in the corresponding slot and the CRC checksum field is updated.

[0063] To ensure efficient readback verification, the master creates and initializes a checksum table next to the ring buffer. The number of entries in the table is equal to the total number of pages, and each entry stores the page index, page CRC, and a valid flag. Once the page access state machine enters the READY state, the read transaction thread triggers EEPROM read commands in a loop, starting with the current page index 0. After each page is moved, the thread calculates the CRC16 of the corresponding slot data in the master buffer and writes it to the checksum table. The page index is incremented until all eight pages have been moved. When the valid flags for all entries in the checksum table are set, the read transaction thread reports a "READ_FINISH" event to the soft programmable logic controller, along with the CRC summary value, for further storage to a file or version comparison by higher-level tasks.

[0064] This embodiment achieves capacity-adaptive page access through dynamic generation of paging descriptors and transaction initiation in the write register mode; bus arbitration locking avoids concurrent interference; buffer mapping and check table mechanism ensures data and index synchronization, significantly improving the organization, reliability and real-time performance of large-capacity EEPROM batch reading and writing.

[0065] In some embodiments, the EEPROM control registers of the target slave stations are triggered sequentially, EEPROM data is read page by page from a starting offset into the master station buffer, and a cyclic redundancy check is performed on each page of data read, including: Determine the EEPROM physical address of the current page according to the paging descriptor, write the EEPROM physical address into the EEPROM address register of the target slave, and set the read command flag in the EEPROM control register; Monitor the busy flag of the EEPROM control register. When the busy flag is reset, the current page data is moved to the position corresponding to the page index in the master buffer through the synchronous management channel. On the master side, a cyclic redundancy check is performed on the current page data after the move, and the obtained check value is compared with the page check field returned by the target slave. If the comparison is consistent, the page index is incremented until all data pages within the access length are read. If the comparison is inconsistent, the paging transaction is terminated immediately and a check exception message is generated.

[0066] Specifically, in the previous embodiment, after the paging access state machine enters the READY state, the read thread begins executing the page-by-page read process. First, the read thread calculates the EEPROM physical address based on the current page index and the number of bytes per page in the paging descriptor: physical address = starting offset + page index × number of bytes per page. In this embodiment, the initial value of the current page index is 0, and the number of bytes per page is 128 bytes, so the physical address of the first page is 0. The read thread writes this physical address to the EEPROM address registers 0x0504-0x0505 of the target slave station and sets the read command flag and start bit in the EEPROM control register 0x0502.

[0067] The CPU enters short polling mode and monitors the Busy flag of the same control register. When the Busy bit is set to 1 by hardware, it indicates that a page read is in progress. When the Busy bit is automatically cleared to 0, the page data has been moved from the ESC to the slave buffer. The read thread then immediately initiates an LRW instruction via the synchronization management channel, moving all 128 bytes of data to slot 0 of the master's ring buffer. After the move is complete, the read thread locally calculates the cyclic redundancy check value for the data in that slot using the CRC16 algorithm with polynomial 0x1021. This calculation is then compared byte-by-byte with the page CRC field returned by the target slave from control register 0x0506.

[0068] If the comparison results are consistent, indicating that the page data is complete and correct, the read thread sets the valid flag for index 0 in the checksum table, increments the page index by one, and proceeds to the next page read. If the comparison results are inconsistent, the read thread immediately resets the start bit of the current paging transaction, writes the difference between the page index and the checksum to the diagnostic log, and reports a "CRC_ERROR" error to the soft programmable logic controller. Upon receiving the error, the state machine automatically releases the slave bus arbitration resources, aborting the paging transaction.

[0069] In the normal process of this embodiment, the read thread sequentially moves and verifies eight pages of data. After all verifications pass, the valid flag for each page is set to 1 in the checksum table. The read thread then writes a completion flag to the paging access state machine, which sets the transaction completion bit in the control register and switches the master state machine to IDLE. The read thread then writes the full ring buffer to the external binary file "IO-E2PROM-Backup.bin" in page order and writes the file path, total number of pages, and aggregated CRC value to the operation log.

[0070] Through the above steps, this embodiment realizes high-speed page-by-page migration and local cyclic redundancy check of the target slave station EEPROM without additionally interrupting the field control cycle, which not only ensures the integrity of large-capacity data, but also can immediately terminate the transaction and issue an abnormal alarm to the upper-level system when the check fails, significantly improving the reliability and security of online backup operations.

[0071] In some embodiments, a data file to be written is read into a buffer of a master station, and is written to an EEPROM of a target slave station in page order starting from a starting offset. After each page is written, the page data is read back and a cyclic redundancy check is performed, including: Split the data file to be written into several pages according to the paging descriptor, write each page of data into the corresponding area of ​​the master buffer according to the page index, and calculate the cyclic redundancy check value for each page; Write the EEPROM physical address of the current page into the EEPROM address register of the target slave, write the current page data into the EEPROM data register, and set the write command flag in the EEPROM control register to start the write operation; Monitor the busy flag of the EEPROM control register. When the busy flag is reset, read back the current page data to the temporary area of ​​the master buffer through the synchronous management channel, perform a cyclic redundancy check on the read-back data, and compare the obtained check value with the cyclic redundancy check value. When the comparison is consistent, the page index is incremented until all pages are written. When the comparison is inconsistent, the paging transaction is immediately terminated, the backup data before writing is restored, and the verification exception information is output.

[0072] Specifically, during a field upgrade, an operations engineer needed to write the operating parameters and firmware calibration coefficients of the integrated I / O module to its internal EEPROM. The upgrade package, "IO-Config-New.bin," was 1024 bytes in size and identical to the paging descriptor generated in the previous example: starting offset 0, access length 1024, number of bytes per page 128, and total number of pages 8. To prevent data loss due to an upgrade failure, the system first completely backed up the existing EEPROM to the file "IO-E2PROM-Backup.bin" before entering the write transaction phase.

[0073] The write transaction thread calls the file parser to read "IO-Config-New.bin" into the master's buffer and splits it into eight page blocks according to the page descriptor. For each page block, the thread calls the CRC16 routine to calculate the cyclic redundancy check value and writes the page data and the corresponding checksum value to a fixed slot in the ring buffer. After preparing all pages, the thread reads the current page index 0 and the 128-byte page byte count from the page descriptor, calculates the EEPROM physical address 0 of the current page, and writes it to the target slave's EEPROM address registers 0x0504-0x0505. The thread then writes the 128-byte data at ring buffer index 0 to the target slave's EEPROM data register 0x0508 and sets the write command flag and start bit in EEPROM control register 0x0502 to trigger the write operation.

[0074] During the write process, the thread monitors the Busy bit. Resetting the Busy bit indicates the end of the page write process within the slave. The write transaction thread then reads back 128 bytes of data at the same physical address via the synchronization management channel to a temporary area in the master's buffer. It then performs a new CRC16 calculation and compares it to the pre-stored checksum. If the comparison matches, the valid flag for index 0 in the checksum table is set, the current page index in the page descriptor is incremented by one, and the next page write process begins. If the comparison does not match, the thread immediately resets the start bit in the control register, canceling the write transaction and calling the rollback routine. The rollback routine uses the original data in "IO-E2PROM-Backup.bin" and writes it back to the EEPROM using the same paging process until all pages pass the checksum. The rollback routine then logs the error code "EE-WRITE-CRC-FAIL" and generates an exception event to the soft programmable logic controller.

[0075] In a normal upgrade scenario, the write transaction thread sequentially completes the write and readback verification of eight pages. After all pages pass verification, the thread sets the "TRANSACTION_FINISH" flag in the EEPROM control register and returns a "WRITE_OK" result code and total transaction time statistics to the soft programmable logic controller. Finally, the thread updates the operation log, recording the new file version number, total number of pages, and aggregated CRC value for subsequent auditing by the operation and maintenance system.

[0076] Through the above steps, this embodiment securely writes the file to be written to the target slave EEPROM page by page, ensuring the reversibility of the original data. Page-by-page readback and cyclic redundancy checking ensure that the written data is byte-for-byte consistent with the source file. If the check fails, the transaction is immediately aborted and the backup is automatically restored, effectively avoiding half-written states and the resulting field failures, significantly improving the security and reliability of online upgrades.

[0077] The following are device embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0078] Figure 4 Schematic diagram of the structure of the EEPROM data reading and writing device based on real-time industrial Ethernet provided by the embodiment of the present application. Figure 4 As shown, the EEPROM data reading and writing device based on real-time industrial Ethernet includes: The loading module 401 is used to load the real-time industrial Ethernet communication dynamic library and establish a real-time industrial Ethernet master station according to a preset media access control address; Scanning module 402, used for scanning the real-time industrial Ethernet during the startup process of the real-time industrial Ethernet master station, obtaining slave link topology information, assigning a logical address to each detected slave station, and generating a slave link information table; Matching module 403, used to match the slave information in the engineering network information file with the slave link information table, and record the physical address and EEPROM capacity parameters of the corresponding target slave in the internal cache when the match is successful; A setting module 404 is used to set the starting offset and access length of the EEPROM access according to the EEPROM capacity parameter on the target slave station to establish a paging transaction; The read module 405 is used to trigger the EEPROM control register of the target slave station in sequence when the paging transaction is of the read type, read the EEPROM data page by page from the starting offset to the master station buffer, and perform a cyclic redundancy check on each page of data read; The write module 406 is used to read the data file to be written into the master station buffer when the paging transaction is of the write type, write the data file to be written into the EEPROM of the target slave station in page order starting from the starting offset, and read back the page data after each page is written and perform a cyclic redundancy check; The output module 407 is configured to output a transaction completion status to the soft programmable logic controller after all page data of a read-type or write-type paging transaction pass a cyclic redundancy check.

[0079] In some embodiments, Figure 4 The loading module 401 mounts the dynamic link library containing the real-time industrial Ethernet protocol stack to the soft programmable logic controller operating environment through the configuration file; parses the target network port media access control address in the configuration file, and obtains the actual media access control address of the device where the soft programmable logic controller is located; compares the target network port media access control address with the actual media access control address, and when the comparison is consistent, enables the original data frame transceiver channel at the corresponding network port and starts the real-time industrial Ethernet master station state machine, and outputs binding exception information and terminates the master station establishment process when the comparison is inconsistent.

[0080] In some embodiments, Figure 4 After the real-time industrial Ethernet master station enters the initialization state, the scanning module 402 continuously sends automatic increment address detection frames to identify the physical address sequence of each slave station in the network in turn; writes a unique logical address to each identified slave station, and reads the slave station's manufacturer identification, product number, serial number and alias information; records the logical address and the corresponding physical address and manufacturer identification, product number, serial number and alias information in the identification order to generate a slave station link information table.

[0081] In some embodiments, Figure 4 The matching module 403 parses the engineering network information file, extracts the manufacturer identification, product number, serial number, alias and expected physical location of each slave station; traverses the slave station link information table, and reads the manufacturer identification, product number, serial number and alias information of the corresponding slave station in the order of the logical address; compares the slave station information in the engineering network information file with the information in the slave station link information table one by one, and determines the target slave station that has been successfully matched when the comparison results are all consistent; reads the EEPROM capacity parameter at the target slave station that has been successfully matched, and writes it into the internal cache together with the physical address of the target slave station; for the slave station with inconsistent comparison results, generates matching exception information and outputs it to the soft programmable logic controller.

[0082] In some embodiments, Figure 4 The setting module 404 calls the transaction configuration subroutine according to the EEPROM capacity parameter, calculates the number of bytes in a single page and the upper limit of the number of pages, and generates a paging descriptor including the starting offset, access length, and the number of bytes in a single page; writes the paging descriptor through the EEPROM control register group of the target slave station, and sets the transaction type identification bit at the same time to start the paging access state machine; after the paging access state machine enters the ready state, it locks the EEPROM bus arbitration resource of the target slave station, and establishes a buffer mapping corresponding to the paging descriptor on the master station side, providing an index and readback verification benchmark for subsequent page reading and writing.

[0083] In some embodiments, Figure 4 The read module 405 determines the EEPROM physical address of the current page according to the paging descriptor, writes the EEPROM physical address into the EEPROM address register of the target slave station, and sets the read command flag in the EEPROM control register; monitors the busy flag of the EEPROM control register, and when it is detected that the busy flag is reset, moves the current page data to the position corresponding to the page index in the master station buffer through the synchronous management channel; performs a cyclic redundancy check on the moved current page data on the master station side, and compares the obtained check value with the page check field returned by the target slave station. If the comparison is consistent, the page index is incremented until all data pages within the access length are read. If the comparison is inconsistent, the paging transaction is immediately terminated and a check exception message is generated.

[0084] In some embodiments, Figure 4 The write module 406 splits the data file to be written into several pages according to the paging descriptor, writes the data of each page into the corresponding area of ​​the master station buffer according to the page index, and calculates a cyclic redundancy check value for each page; writes the EEPROM physical address of the current page into the EEPROM address register of the target slave station, writes the current page data into the EEPROM data register, and sets the write command flag in the EEPROM control register to start the write operation; monitors the busy flag of the EEPROM control register, and when the busy flag is reset, reads back the current page data to the temporary area of ​​the master station buffer through the synchronous management channel, performs a cyclic redundancy check on the read-back data, and compares the obtained check value with the cyclic redundancy check value; when the comparison is consistent, the page index is incremented until all pages are written. When the comparison is inconsistent, the paging transaction is immediately terminated, the backup data before writing is restored, and the check exception information is output.

[0085] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0086] Figure 5 Schematic diagram of the electronic device 5 provided in the embodiment of the present application. Figure 5 As shown, the electronic device 5 of this embodiment includes: a processor 501, a memory 502, and a computer program 503 stored in the memory 502 and executable by the processor 501. When the processor 501 executes the computer program 503, the steps of the above-mentioned method embodiments are implemented. Alternatively, when the processor 501 executes the computer program 503, the functions of the modules / units in the above-mentioned device embodiments are implemented.

[0087] The electronic device 5 may be a desktop computer, a notebook, a PDA, a cloud server, or other electronic device. The electronic device 5 may include but is not limited to a processor 501 and a memory 502. Those skilled in the art will appreciate that Figure 5 This is merely an example of the electronic device 5 and does not limit the electronic device 5 . The electronic device 5 may include more or fewer components than shown in the figure, or different components.

[0088] The processor 501 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0089] The memory 502 can be an internal storage unit of the electronic device 5, such as a hard drive or memory of the electronic device 5. The memory 502 can also be an external storage device of the electronic device 5, such as a plug-in hard drive, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. The memory 502 can also include both an internal storage unit of the electronic device 5 and an external storage device. The memory 502 is used to store computer programs and other programs and data required by the electronic device.

[0090] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0091] If the integrated modules / units are implemented as software functional units and sold or used as independent products, they can be stored in a readable storage medium (e.g., a computer-readable storage medium). Based on this understanding, the present application can implement all or part of the process steps in the above-mentioned method embodiments by using a computer program to instruct the relevant hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program can include computer program code, which can be in source code form, object code form, executable file, or some intermediate form. Computer-readable storage media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, removable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunications signals, and software distribution media.

[0092] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.< / device> < / device> < / device>

Claims

1. A method for reading and writing EEPROM data based on real-time industrial Ethernet, characterized in that: include: Load the real-time industrial Ethernet communication dynamic library and establish a real-time industrial Ethernet master station according to the preset media access control address; During the startup of the real-time industrial Ethernet master station, the real-time industrial Ethernet is scanned to obtain slave link topology information, a logical address is assigned to each detected slave station, and a slave link information table is generated; Matching the slave station information in the engineering network information file with the slave station link information table, and recording the physical address and EEPROM capacity parameters of the corresponding target slave station in the internal cache when the match is successful; Setting the starting offset and access length of EEPROM access according to the EEPROM capacity parameter on the target slave station to establish a paging transaction; When the paging transaction is of a read type, triggering the EEPROM control register of the target slave station in sequence, reading EEPROM data page by page from the starting offset to the master station buffer, and performing a cyclic redundancy check on each page of data read; When the paging transaction is of a write type, the data file to be written is read into the master station buffer, and is written into the EEPROM of the target slave station in page order starting from the starting offset, and after each page is written, the page data is read back and a cyclic redundancy check is performed; When all page data of the read-type or write-type paging transaction pass the cyclic redundancy check, the transaction completion status is output to the soft programmable logic controller.

2. The method according to claim 1, characterized in that The method of loading a real-time industrial Ethernet communication dynamic library and establishing a real-time industrial Ethernet master station according to a preset media access control address includes: Mount the dynamic link library containing the real-time industrial Ethernet protocol stack to the soft programmable logic controller operating environment through the configuration file; Parsing the target network port media access control address in the configuration file and obtaining the actual media access control address of the device where the soft programmable logic controller is located; The target network port media access control address is compared with the actual media access control address. When the comparison is consistent, the original data frame transceiver channel is enabled at the corresponding network port and the real-time industrial Ethernet master station state machine is started. When the comparison is inconsistent, the binding exception information is output and the master station establishment process is terminated.

3. The method according to claim 1, characterized in that The method of scanning the real-time industrial Ethernet to obtain slave link topology information, assigning a logical address to each detected slave, and generating a slave link information table includes: After the real-time industrial Ethernet master enters the initialization state, it continuously sends auto-increment address detection frames to identify the physical address sequence of each slave station in the network; Write a unique logical address to each identified slave station and read the slave station's manufacturer identification, product number, serial number and alias information; The logical address and the corresponding physical address as well as the manufacturer identification, product number, serial number and alias information are recorded in an identification order to generate the slave station link information table.

4. The method according to claim 1, wherein The slave station information in the engineering network information file is matched with the slave station link information table, and when the match is successful, the physical address and EEPROM capacity parameters of the corresponding target slave station are recorded in the internal cache, including: Parse the engineering network information file to extract the manufacturer identification, product number, serial number, alias, and expected physical location of each slave station; Traversing the slave station link information table, reading the manufacturer identification, product number, serial number and alias information of the corresponding slave station in logical address order; Compare the slave station information in the engineering network information file with the information in the slave station link information table one by one, and determine the target slave station that is successfully matched when the comparison results are all consistent; Read the EEPROM capacity parameter at the successfully matched target slave station and write it into the internal cache together with the physical address of the target slave station; For slaves with inconsistent comparison results, matching exception information is generated and output to the soft programmable logic controller.

5. The method according to claim 1, wherein The step of setting the starting offset and access length of the EEPROM access according to the EEPROM capacity parameter on the target slave station to establish a paging transaction includes: Calling a transaction configuration subroutine according to the EEPROM capacity parameter, calculating the number of bytes in a single page and the upper limit of the number of pages, and generating a paging descriptor including a starting offset, an access length, and the number of bytes in a single page; Writing the paging descriptor through the EEPROM control register group of the target slave station and setting the transaction type identification bit to start the paging access state machine; After the paging access state machine enters the ready state, the EEPROM bus arbitration resource of the target slave is locked, and a buffer mapping corresponding to the paging descriptor is established on the master side to provide an index and readback verification benchmark for subsequent page reading and writing.

6. The method according to claim 1, characterized in that The method of sequentially triggering the EEPROM control register of the target slave station, reading EEPROM data from the starting offset to the master station buffer by page, and performing a cyclic redundancy check on each page of data read includes: Determine the EEPROM physical address of the current page according to the paging descriptor, write the EEPROM physical address into the EEPROM address register of the target slave, and set the read command flag in the EEPROM control register; Monitoring the busy flag of the EEPROM control register, and when detecting that the busy flag is reset, moving the current page data to a position corresponding to the page index in the master buffer through the synchronous management channel; On the master station side, a cyclic redundancy check is performed on the current page data after the move, and the obtained check value is compared with the page check field returned by the target slave station. When the comparison is consistent, the page index is incremented until all data pages within the access length are read. When the comparison is inconsistent, the paging transaction is immediately terminated and a check exception message is generated.

7. The method according to claim 1, characterized in that The method comprises: reading the data file to be written into the master station buffer, writing the data file to the EEPROM of the target slave station in page order starting from the starting offset, and reading back the page data after each page is written and performing a cyclic redundancy check. Split the data file to be written into several pages according to the paging descriptor, write each page of data into the corresponding area of ​​the master buffer according to the page index, and calculate the cyclic redundancy check value for each page; Write the EEPROM physical address of the current page into the EEPROM address register of the target slave, write the current page data into the EEPROM data register, and set the write command flag in the EEPROM control register to start the write operation; monitoring a busy flag of the EEPROM control register, and when the busy flag is reset, reading back the current page data to a temporary area of ​​the master buffer through a synchronous management channel, performing a cyclic redundancy check on the read-back data, and comparing the obtained check value with the cyclic redundancy check value; When the comparison is consistent, the page index is incremented until all pages are written. When the comparison is inconsistent, the paging transaction is immediately terminated, the backup data before writing is restored, and verification exception information is output.

8. An EEPROM data reading and writing device based on real-time industrial Ethernet, characterized in that: include: A loading module is used to load a real-time industrial Ethernet communication dynamic library and establish a real-time industrial Ethernet master station according to a preset media access control address; A scanning module is used to scan the real-time industrial Ethernet during the startup process of the real-time industrial Ethernet master station, obtain the slave station link topology information, assign a logical address to each detected slave station, and generate a slave station link information table; A matching module is used to match the slave station information in the engineering network information file with the slave station link information table, and record the physical address and EEPROM capacity parameters of the corresponding target slave station in the internal cache when the match is successful; A setting module is used to set the starting offset and access length of EEPROM access according to the EEPROM capacity parameter on the target slave station to establish a paging transaction; a reading module, configured to, when the paging transaction is of a read type, sequentially trigger the EEPROM control register of the target slave station, read EEPROM data page by page from the starting offset into the master station buffer, and perform a cyclic redundancy check on each page of data read; a write module configured to read the data file to be written into the master station buffer when the paging transaction is of a write type, write the data file into the EEPROM of the target slave station in page order starting from the starting offset, and read back the page data after each page is written and perform a cyclic redundancy check; The output module is used to output a transaction completion status to the soft programmable logic controller after all page data of the read type or write type paging transaction pass the cyclic redundancy check.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images