Scheduling circuit, method and unit, processing system, equipment and medium

Abstract

The invention provides a scheduling circuit, method and unit, a processing system, equipment and a medium, and belongs to the technical field of computers. The scheduling circuit comprises a plurality of strategy arbiters, a control register and a selector, wherein different strategy arbiters correspond to different preset scheduling strategies; any strategy arbiter is used for selecting a second thread bundle matched with a preset scheduling strategy of the strategy arbiter from the plurality of first thread bundles according to the state information of the plurality of first thread bundles; and the selector is used for selecting a target thread bundle from a plurality of second thread bundles determined based on the plurality of strategy arbiters according to a control signal of the control register so as to schedule the target thread bundle to execute data processing, and the control signal is determined according to program characteristics of processing programs corresponding to the plurality of first thread bundles. According to the embodiment of the invention, the target thread bundle better matched with the program characteristics can be screened out, the scheduling effect is improved, and then the program execution performance is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and particularly to a scheduling circuit, a scheduling method, a scheduling unit, a processing system, an electronic device, and a computer-readable storage medium. Background Art

[0002] A warp is a basic execution unit in some processing architectures and consists of multiple threads. Usually, a scheduling unit is required to select one or more warps from multiple warps and send them to an execution unit to perform corresponding data processing.

[0003] In related technologies, polling scheduling strategies, priority scheduling strategies, etc. can be used to schedule warps to complete corresponding processing programs. Among them, the polling scheduling strategy can give each warp an even execution opportunity, but it has a low tolerance for long-delay operations; the priority scheduling strategy can ensure that high-priority tasks are executed first, but it may cause long waiting times for low-priority tasks. In other words, no matter which scheduling strategy is adopted, it can only improve the scheduling effect in some aspects, and the scheduling methods in related technologies cannot meet the requirements of multiple types of processing programs and will affect the execution performance of the processing programs. Summary of the Invention

[0004] The present disclosure provides a scheduling circuit, a scheduling method, a scheduling unit, a processing system, an electronic device, and a computer-readable storage medium.

[0005] In a first aspect, the present disclosure provides a scheduling circuit, which includes: a plurality of policy arbitrators, a control register, and a selector. Different policy arbitrators correspond to different preset scheduling strategies; any one of the policy arbitrators is configured to select a second warp that matches the preset scheduling strategy of the policy arbitrator from a plurality of first warps according to the status information of the plurality of first warps; the selector is configured to select a target warp from the plurality of second warps determined based on the plurality of policy arbitrators according to the control signal of the control register to schedule the target warp to perform data processing, and the control signal is determined according to the program characteristics of the processing programs corresponding to the plurality of first warps.

[0006] In a second aspect, the present disclosure provides a scheduling method, which includes: selecting a second warp that matches each preset scheduling strategy from a plurality of first warps according to the status information of the plurality of first warps, where the number of the preset scheduling strategies is multiple and the multiple preset scheduling strategies are different; selecting a target warp from the second warps that match each preset scheduling strategy according to the program characteristics of the processing programs corresponding to the plurality of first warps to schedule the target warp to perform data processing.

[0007] In a third aspect, the present disclosure provides a scheduling unit, which includes a scheduling circuit and a sending circuit; wherein, the sending circuit is configured to send a target warp determined by the scheduling circuit to a preset processor, and the scheduling circuit adopts the scheduling circuit according to any one of the embodiments of the present disclosure.

[0008] In a fourth aspect, the present disclosure provides a processing system, which includes at least one scheduling unit and at least one processing unit; wherein, the processing unit is configured to perform data processing according to a target warp, and the scheduling unit adopts the scheduling unit according to any one of the embodiments of the present disclosure.

[0009] In a fifth aspect, the present disclosure provides an electronic device, which includes at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor so that the at least one processor can execute the above-mentioned scheduling method.

[0010] In a sixth aspect, the present disclosure provides a computer-readable storage medium, on which a computer program is stored, wherein, the computer program realizes the above-mentioned scheduling method when being executed by a processor.

[0011] In the embodiments provided by the present disclosure, corresponding policy arbitrators are configured for different preset scheduling policies, so that second warps matching each preset scheduling policy (or policy arbitrator) can be screened out from multiple first warps in parallel, such that the multiple second warps screened out incorporate the characteristics of different preset scheduling policies. On this basis, control signals of a control register can be determined according to the program characteristics of the processing programs corresponding to the multiple first warps, and thus target warps that are more matched with the program characteristics can be further screened out from the multiple second warps, improving the scheduling effect and further improving the program execution performance.

[0012] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understandable through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification. They are used to explain the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation to the present disclosure. By referring to the drawings to describe the detailed exemplary embodiments, the above and other features and advantages will become more obvious to those skilled in the art. In the drawings:

[0014] Figure 1Schematic diagram of a scheduling circuit provided by an embodiment of the present disclosure.

[0015] Figure 2 Schematic diagram of the execution process of a first scheduling strategy provided by an embodiment of the present disclosure.

[0016] Figure 3 Schematic diagram of the execution process of a second scheduling strategy provided by an embodiment of the present disclosure.

[0017] Figure 4 Schematic diagram of a scheduling circuit provided by an embodiment of the present disclosure.

[0018] Figure 5 Schematic diagram of the execution process of a first scheduling strategy provided by an embodiment of the present disclosure.

[0019] Figure 6 Flowchart of a scheduling method provided by an embodiment of the present disclosure.

[0020] Figure 7 Schematic diagram of a scheduling unit provided by an embodiment of the present disclosure.

[0021] Figure 8 Schematic diagram of a processing system provided by an embodiment of the present disclosure.

[0022] Figure 9 Block diagram of an electronic device provided by an embodiment of the present disclosure.

[0023] Figure 10 Block diagram of an electronic device provided by an embodiment of the present disclosure. Detailed implementation manners

[0024] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the following provides descriptions of exemplary embodiments of the present disclosure with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to assist in understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted below.

[0025] Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0026] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] The terms used herein are for describing particular embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms "comprises" and / or "consists of" are used in this specification, it specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0029] In architectures such as Single Instruction Multiple Threads (SIMT), multiple threads form a warp, and multiple warps increase parallelism and hide execution latency through scheduled execution. In other words, the responsibility of scheduling is to select one or more warps from the ready warps and send them to the idle execution units. Since this process connects two key steps of instruction fetching and execution, the scheduling selection of warps will involve multiple aspects of the execution process of the entire processing system and has an important impact on its performance.

[0030] In the related art, each warp judges in parallel whether the current instruction is ready. In a processor, a ready instruction needs to meet three basic conditions: the instruction has been fetched, all dependencies of the instruction have been resolved, and the execution unit corresponding to the instruction is available. A warp that meets the above three basic conditions can be considered issuable and can participate in scheduling.

[0031] Furthermore, in the related art, the scheduling circuit usually only supports a single scheduling strategy. While different scheduling strategies have their advantages, they also have certain limitations. Therefore, the warps selected based on this scheduling circuit are restricted by its scheduling strategy itself and may not always meet the usage requirements or may not always give the optimal scheduling scheme.

[0032] In view of this, embodiments of the present disclosure provide a scheduling circuit, a scheduling method, a scheduling unit, a processing system, an electronic device, and a computer-readable storage medium. Corresponding policy arbitrators are configured for different preset scheduling policies, so that second thread bundles matching each preset scheduling policy (or policy arbitrator) can be screened out from multiple first thread bundles in parallel, such that the multiple second thread bundles screened out incorporate the characteristics of different preset scheduling policies. On this basis, control signals of a control register can be determined according to the program characteristics of the processing programs corresponding to the multiple first thread bundles, and thus target thread bundles that are more matched with the program characteristics can be further screened out from the multiple second thread bundles by using the control signals, improving the scheduling effect and further improving the program execution performance.

[0033] In a first aspect of embodiments of the present disclosure, a scheduling circuit is provided.

[0034] Figure 1 is a schematic diagram of a scheduling circuit provided by embodiments of the present disclosure. Referring to Figure 1 , the scheduling circuit 100 may include: a plurality of policy arbitrators (such as policy arbitrator 1101, ……, policy arbitrator 110M, M>1), a control register 120, and a selector 130. Different policy arbitrators correspond to different preset scheduling policies.

[0035] Any one of the policy arbitrators is configured to select, according to the status information of multiple first thread bundles, a second thread bundle that matches the preset scheduling policy of the policy arbitrator from the multiple first thread bundles.

[0036] The selector 130 is configured to select a target thread bundle from the multiple second thread bundles determined based on the plurality of policy arbitrators according to the control signal of the control register 120, so as to schedule the target thread bundle to execute data processing. The control signal is determined according to the program characteristics of the processing programs corresponding to the multiple first thread bundles.

[0037] In some optional embodiments, the output end of the policy arbitrator and the output end of the control register 120 are both connected to the input end of the selector 130. On the one hand, it can enable the selector to clarify the second thread bundles selected by each policy arbitrator and matching its preset scheduling policy, and on the other hand, it can enable the selector 130 to receive the control signal sent by the control register 120, so as to select a target thread bundle from the multiple second thread bundles determined based on the plurality of policy arbitrators according to the control signal.

[0038] In the embodiments provided by the present disclosure, corresponding policy arbitrators are configured for different preset scheduling policies, so that second warps matching each preset scheduling policy (or policy arbitrator) can be screened out from multiple first warps in parallel, enabling the multiple second warps screened out to incorporate the characteristics of different preset scheduling policies. On this basis, the control signals of the control registers can be determined according to the program characteristics of the handlers corresponding to the multiple first warps, and then the target warps that better match the program characteristics can be screened out from the multiple second warps by using the control signals, improving the scheduling effect and thus enhancing the program execution performance.

[0039] It can be seen from this that in the embodiments of the present disclosure, for the scheduling of warps, multiple preset scheduling policies are determined in advance, and corresponding policy arbitrators are set for each preset scheduling policy. Based on this, each policy arbitrator can select the second warps that match the corresponding preset scheduling policy according to the preset scheduling policy. The second warps selected by the multiple policy arbitrators incorporate the scheduling advantages of each preset scheduling policy, providing multiple options. On this basis, the control signals of the control registers can be determined according to the program characteristics, and then the target warps that better match the program characteristics can be further screened out from the multiple second warps based on the control signals and through a selector, so that the target warps can be scheduled to execute corresponding data processing (such as data calculation or data access, etc.), thereby improving the program execution performance.

[0040] The scheduling circuit of the embodiments of the present disclosure will be described in detail below.

[0041] In some alternative embodiments, multiple threads can form a warp.

[0042] Exemplarily, 32 consecutive threads can form a warp. Moreover, in the SIMT architecture, all threads in a warp execute the same instruction, and each thread operates on private data.

[0043] As mentioned above, parallelism can be increased and execution latency can be hidden by scheduling the execution among multiple warps. In some alternative embodiments, some status information of the warps can be used to select the warps to be scheduled. Among them, the status information can represent some attribute information of the warps.

[0044] For example, the status information can reflect whether the first warp is ready, whether the first warp is valid, when the first warp enters the waiting queue, etc. The embodiments of the present disclosure do not limit this. Among them, if all the preconditions of the first warp are met, it is determined that the first warp is ready. The preconditions include that the required data has been loaded and the resources have been properly allocated, etc. Whether the first warp is valid can indicate whether the first warp is in an available state. Correspondingly, there may be some disabled first warps, and these disabled first warps are in an unavailable state.

[0045] In some alternative embodiments, the status information of the first warp includes the ready status information and the waiting status information of the first warp. Among them, the ready status information is used to indicate whether the first warp is in a ready state or an unready state, and the waiting status information is used to indicate the order in which the first warp enters the scheduling waiting state. Among them, the order in which the first warp enters the scheduling waiting state can be represented as the order in which the first warp enters the waiting queue.

[0046] In some alternative embodiments, the ready status information can be characterized based on a ready mask.

[0047] Exemplarily, the ready mask corresponding to the first warp includes a first bit value, and the first bit value is used to characterize whether the corresponding first warp is in a ready state or an unready state.

[0048] In some alternative embodiments, the ready masks corresponding to N first warps are a bit string including N first bit values, where N is an integer greater than 1.

[0049] For example, the first bit value includes two cases of "0" and "1", and it is predefined that when the first bit value is "0", it characterizes that the corresponding first warp is in an unready state, and when the first bit value is "1", it characterizes that the corresponding first warp is in a ready state. Based on this, when the first bit value corresponding to the first warp is clear, it can be determined whether the first warp is in a ready state or an unready state. Taking 3 first warps as an example, if the corresponding ready mask is 111, it means that these 3 first warps are all in a ready state.

[0050] It should be noted that the above representation methods for the ready state are only examples, and the embodiments of the present disclosure do not limit this.

[0051] In some alternative embodiments, the waiting status information can be characterized based on a waiting mask.

[0052] Exemplarily, the wait mask corresponding to the first warp includes a second bit value, and the second bit value is used to indicate whether the first warp corresponding to the second bit value is in a scheduling wait state before the current warp.

[0053] Exemplarily, the wait state information of any one of the first warps is represented by a wait mask. That is, if the number of the first warps is N, there are N wait masks, and the N wait masks correspond to the N first warps one by one, where N is an integer greater than 1. For the wait mask of the current warp among the N first warps, the wait mask includes N second bit values corresponding to the N first warps, and the second bit value is used to indicate whether the corresponding first warp is in a scheduling wait state before the current warp. Among them, the second bit value corresponding to the current warp in the wait mask can use a preset value, and the preset value can be the same as the value of the second bit value corresponding to the first warp that enters the scheduling wait state later than the current warp.

[0054] For example, if there are 4 first warps, namely warp 0, warp 1, warp 2, and warp 3, the wait mask corresponding to each first warp includes 4 second bit values, which can be represented as b3b2b1b0. Among them, the rightmost second bit value b0 in the wait mask corresponds to warp 0, the second bit value b1 corresponds to warp 1, the second bit value b2 corresponds to warp 2, and the second bit value b3 corresponds to warp 3. And it is pre-specified that when the second bit value is "1", it indicates that the first warp corresponding to the second bit value enters the scheduling wait state before the current warp, and when the second bit value is "0", it indicates that the corresponding first warp enters the scheduling wait state later than the current warp (the second bit value corresponding to the current warp is also "0"). If the current warp is warp 1 and its wait mask is 1000, since only the second bit value corresponding to warp 3 in the wait mask is 1 and the second bit values corresponding to other first warps are 0, therefore, this wait mask indicates that warp 3 enters the scheduling wait state before warp 1, and other warps enter the scheduling wait state after warp 1.

[0055] In some alternative embodiments, the wait mask is a mask generated according to the first warps that enter the scheduling wait state before the current warp when the current warp first enters the scheduling wait state.

[0056] In other words, for any one of the first warps, when it first enters the scheduling wait state, it can be determined which first warps have entered the scheduling wait state. Based on this, the wait mask corresponding to the first warp can be generated.

[0057] Still taking the above 4-bit waiting mask as an example, if warp 1 is in the scheduling waiting state for the first time, warp 3 is already in the scheduling waiting state, and warps 0 and 2 have not entered the scheduling waiting state yet, then the waiting mask 1000 corresponding to warp 1 can be generated.

[0058] In some alternative embodiments, the waiting state information may also be characterized by the timestamp when the first warp enters the scheduling waiting state, the sequence number when the first warp enters the scheduling waiting state, etc., and the embodiments of the present disclosure do not limit this.

[0059] In some alternative embodiments, the preset scheduling policy includes at least a first scheduling policy. The first scheduling policy (Ready-Then-Oldest, RTO) is used to use the first warp that is in the ready state and is the first to be in the scheduling waiting state as the second warp. The policy arbiter corresponding to the first scheduling policy is used to perform preset logical processing on the ready mask and the waiting masks corresponding to each first warp to obtain an arbitration result, and the arbitration result is used to indicate the second warp that matches the first scheduling policy.

[0060] In some alternative embodiments, the preset scheduling policy may also include a second scheduling policy based on round-robin (RR). The second scheduling policy sequentially selects the first warps in the ready state for scheduling. In other words, the second scheduling policy assigns the same priority to multiple first warps in the ready state and sequentially selects these first warps for scheduling. The policy arbiter corresponding to the second scheduling policy is then used to select the second warp that matches the second scheduling policy from multiple first warps.

[0061] Figure 2 It is a schematic diagram of the execution process of a first scheduling policy provided by the embodiments of the present disclosure. Refer to Figure 2 It shows the processing process of scheduling the above first warp based on the first scheduling policy.

[0062] Exemplarily, if there are multiple first warps (such as W0, W1, W2...), all of which are in the ready state and enter the scheduling waiting state in sequence (that is, W0 enters the scheduling waiting state first, followed by W1, and so on); among them, I0 to Ik-1 in each first warp are arithmetic instructions, and Ik is a memory access instruction. If the first scheduling policy is adopted, it first executes the first warp W0 from the computational instruction I0 to the memory access instruction Ik, and then executes the instructions of the first warp W1 until Ik, and so on, until the instructions of the last first warp Ik are executed.

[0063] Figure 3 It is a schematic diagram of the execution process of a second scheduling policy provided by the embodiments of the present disclosure. Refer to Figure 3, which shows the processing process of scheduling multiple first warps (such as 16 first warps) based on the second scheduling policy. For 16 first warps, it sequentially schedules the I0 of each first warp, and after 16 cycles, it sequentially schedules the instruction I1 of each first warp. Repeat the above process until the instruction Ik of all first warps is scheduled.

[0064] It can be seen from Figure 3 that when all first warps start to enter the Ik instruction, there are no more first warps available for scheduling to hide the memory access latency, resulting in the computing unit being idle for a relatively long time, which reflects that the second scheduling policy has a relatively low tolerance for long-latency operations.

[0065] Furthermore, by comparing Figure 2 and Figure 3 it can be known that the idle duration corresponding to the computing unit in the first scheduling policy is less than that in the second scheduling policy. Therefore, for the processing program corresponding to the above multiple first warps, adopting the first scheduling policy can reduce the idle time of the computing unit to a certain extent.

[0066] It can be seen from this that for different program characteristics, selecting different preset scheduling policies will have different impacts on the program execution performance. Therefore, after determining the second warps corresponding to each preset scheduling policy, the control signal determined based on the program characteristics can be used to further screen out the second warps that are more matched with the program characteristics from multiple second warps as the target warps to be issued.

[0067] In some alternative embodiments, the preset scheduling policy may further include a third scheduling policy based on Greedy-Then-Oldest (GTO). The third scheduling policy will preferentially select the current first warp for scheduling, that is, the execution sequence always corresponds to the current first warp until the first warp cannot be executed due to data dependencies or other reasons, and then the first warp that is in the scheduling waiting state (Oldest) for the longest time will be re-selected for scheduling. The policy arbiter corresponding to the third scheduling policy is used to select the second warp that matches the third scheduling policy from multiple first warps.

[0068] It should be noted that the above is only an example of the preset scheduling policy, and the present disclosure embodiments do not limit the number and type of the preset scheduling policies.

[0069] Figure 4 This is a schematic diagram of a scheduling circuit provided by the embodiments of the present disclosure. Refer to Figure 4, first, the instruction request is sent to the instruction cache (I-Cache) through the instruction fetch unit (I-Fetch). For the instruction cache, if the request from the instruction fetch unit is hit in the instruction cache, the corresponding instruction is transmitted to the decode unit (Decode). The decode unit decodes the instruction on one hand and forwards the decoded instruction to the instruction buffer (I-Buffer), using the instruction buffer to save the decoded instruction information of all warps. On the other hand, the source and register information is forwarded to the scoreboard. The scoreboard is used to support instruction-level parallelism. That is, when multiple independent instructions are executed in parallel, the scoreboard tracks the write status of the suspended registers to avoid repeated writes. Further, based on the instruction buffer and the scoreboard, the status information of multiple first warps is transmitted to the scheduling circuit 400, and the scheduling circuit 400 performs the scheduling process of multiple first warps to determine and launch the target warp. After the scheduling circuit 400 launches the target warp to the operand collector (Operand Collector, OC), all source operands are collected in the OC stage, and then the corresponding instructions of the target warp are sent to the computing unit or the memory access unit based on the source operands to perform the corresponding data processing.

[0070] Further, as Figure 4 shown, in the scheduling circuit 400, there are M policy arbitrators (such as policy arbitrator 4101,..., policy arbitrator 410M, M is an integer greater than 1), a control register 420, and a selector 430; among them, the output terminals of each policy arbitrator are connected to the input terminal of the selector 430, and the output terminal of the control register 420 is also connected to the input terminal of the selector 430.

[0071] The total number of the first warps is N, and the status information of the N first warps is as Figure 4 shown in the table: The first column of the table corresponds to the serial number identifier of the first warp, including 0, 1, 2,..., N-1; the second column corresponds to the valid status information of the first warp, including the valid status bit values valid(0), valid(1), valid(2),..., valid(N-1) of each first warp; the third column corresponds to the ready status information of the first warp, including the first bit values ready(0), ready(1), ready(2),..., ready(N-1) of each first warp; the fourth column corresponds to the waiting status information of the first warp, including the waiting masks age mask(0), age mask(1), age mask(2),..., age mask(N-1) of each first warp.

[0072] For any policy arbiter, based on the state information of the foregoing first warp and based on the corresponding preset scheduling policy, it screens out the second warp that matches its preset scheduling policy from multiple first warps and generates a corresponding arbitration result, which is used to indicate the second warp that matches the corresponding preset scheduling policy. Among them, the arbitration result may include forms such as the identifier of the second warp or an arbitration mask for indicating the second warp from multiple first warps. The embodiments of the present disclosure do not limit this.

[0073] The selector 430 further screens out the target warp from the multiple second warps corresponding to the multiple arbitration results according to the control signal of the control register 420 and emits the target warp to perform corresponding data processing based on the target warp. Among them, the control signal is determined according to the program characteristics of the processing programs corresponding to the multiple first warps. Therefore, the selected target warp is the most matched with the program characteristics compared with the unselected second warps, thereby effectively improving the program execution performance.

[0074] In some optional embodiments, the preset scheduling policy may be implemented based on an arbiter. Among them, an arbiter is an important functional unit in a digital circuit, which is usually used to decide which request will be allowed and obtain access rights when there are multiple modules in the system that need to access shared resources. Returning to the embodiments of the present disclosure, the policy arbiter is a functional unit for determining the scheduled warp (i.e., the second warp) based on the corresponding preset scheduling policy. In other words, a corresponding preset scheduling policy is configured in the policy arbiter, which enables the policy arbiter to select a first warp that matches the preset scheduling policy from multiple first warps as the second warp based on the configured preset scheduling policy, thereby realizing the scheduling selection of the first warps. And, in the embodiments of the present disclosure, multiple policy arbiters are provided, and different policy arbiters are configured with different preset scheduling policies, so as to be able to determine multiple second warps, and each second warp matches a preset scheduling policy.

[0075] In some optional embodiments, the policy arbiter corresponding to the first scheduling policy is used to arbitrate multiple first warps based on the first scheduling policy according to the ready state information and waiting state information of the multiple first warps, determine the second warp, and generate an arbitration result for indicating the second warp, and send the arbitration result to the selector. Among them, the arbitration result may include at least one of information such as the name of the second warp, the warp identifier, and an arbitration mask for indicating the second warp from multiple first warps, as long as it can clearly identify which first warp is selected as the second warp that matches the first scheduling policy based on the arbitration result.

[0076] Further, considering that the first scheduling policy is used to select the first warp that is in the ready state and the first to be in the scheduling waiting state as the second warp, therefore, the policy arbiter corresponding to the first scheduling policy essentially selects, from multiple first warps, the first warp that is in the ready state and the first to be in the scheduling waiting state according to the ready state information and waiting state information of the multiple first warps, uses this first warp as the second warp that matches the first scheduling policy, and generates an arbitration result for indicating the second warp.

[0077] In some alternative embodiments, the policy arbiter corresponding to the second scheduling policy is configured to arbitrate multiple first warps based on the second scheduling policy according to the ready state information and waiting state information of the multiple first warps, determine the second warp that matches the second scheduling policy, generate an arbitration result for indicating the second warp, and send the arbitration result to the selector. Among them, the second warp that matches the second scheduling policy is the first warp that is in the ready state and is exactly arranged in the current first position (that is, the first warp that is in the ready state and is the first after the previously determined second warp).

[0078] In some alternative embodiments, the policy arbiter corresponding to the third scheduling policy is configured to arbitrate multiple first warps based on the third scheduling policy according to the ready state information and waiting state information of the multiple first warps, determine the second warp that matches the third scheduling policy, generate an arbitration result for indicating the second warp, and send the arbitration result to the selector. Among them, the second warp that matches the third scheduling policy can be the current first warp (which is in the ready state), or it can be the first warp that is the first to be in the scheduling waiting state when the current first warp cannot execute.

[0079] In some alternative embodiments, the policy arbiter corresponding to the first scheduling policy is configured to perform a preset logical process on the ready mask and the waiting masks corresponding to each first warp to obtain an arbitration result, and the arbitration result is used to indicate the second warp that matches the first scheduling policy based on the first scheduling policy. Among them, the preset logical process includes some logical operations such as "OR", "AND", "NOT (inversion)", etc.

[0080] That is to say, by performing a preset logical process on the ready mask and the waiting masks, the first warp that is already in the ready state and the first to enter the scheduling waiting state can be screened out from multiple first warps, so as to determine this first warp as the second warp that matches the first scheduling policy.

[0081] It should be noted that the above preset logical processing for multiple first thread bundles can be parallel, that is, the result bit values of each first thread bundle are determined in parallel, and then the second thread bundles that match the first scheduling policy are screened out from them, so as to improve the scheduling efficiency through this parallel method.

[0082] In some optional embodiments, a policy arbiter corresponding to the first scheduling policy is used to perform the following processing: for any first thread bundle, perform a first logical processing on the ready mask and the wait mask of the first thread bundle to obtain a first intermediate bit value corresponding to the first thread bundle, and the first intermediate bit value is used to indicate whether there is a first thread bundle that is in the ready state and enters the scheduling waiting state earlier than the first thread bundle;

[0083] If the first intermediate bit value indicates that there is a first thread bundle that is in the ready state and enters the scheduling waiting state earlier than the first thread bundle, it is determined that the first thread bundle is not a second thread bundle; if the first intermediate bit value indicates that there is no first thread bundle that is in the ready state and enters the scheduling waiting state earlier than the first thread bundle, the ready state of the first thread bundle is determined according to the first bit value corresponding to the first thread bundle; when it is determined that the first thread bundle is in the ready state based on the first bit value, it is determined that the first thread bundle is a second thread bundle that matches the first scheduling policy; when it is determined that the first thread bundle is in the unready state based on the first bit value, it is determined that the first thread bundle is not a second thread bundle that matches the first scheduling policy.

[0084] It can be seen that the arbitration process for the policy arbiter corresponding to the first scheduling policy can be divided into the above-mentioned multiple steps. First, for any first warp wi, the first step corresponds to the first logical processing. Through the first logical processing, it can be determined whether there is a first warp that is in the ready state and enters the scheduling waiting state earlier than the first warp wi. If there is a first warp that meets the above requirements, it means that the first warp wi is definitely not the second warp, so the first warp wi is excluded; if there is no first warp that meets the above requirements, the first warp wi may or may not be the second warp, mainly depending on whether the first warp wi itself is already in the ready state. Based on this, the ready state of the first warp wi can be determined according to the first bit value corresponding to the first warp wi. If it is determined according to the first bit value that the first warp wi is in the ready state, it means that the first warp wi is the warp that is in the ready state and enters the scheduling waiting state first among the multiple first warps. Therefore, it is determined that the first warp wi is the second warp that matches the first scheduling policy; if it is determined according to the first bit value that the first warp wi is in the unready state, it means that although the first warp wi is the warp that enters the scheduling waiting state first among the multiple first warps, the first warp wi is not yet ready. Therefore, it is determined that the first warp wi is not the second warp that matches the first scheduling policy.

[0085] In some optional embodiments, the first logical processing may include an AND operation and an OR operation. Correspondingly, performing the first logical processing on the ready mask and the waiting mask of the first warp to obtain a first intermediate bit value corresponding to the first warp includes: performing an AND operation on the ready mask and the waiting mask of the first warp to obtain a first intermediate mask corresponding to the first warp; performing an OR operation on the multiple bit values of the first intermediate mask to obtain a first intermediate bit value corresponding to the first warp. Wherein, the number of bits of the ready mask is the same as the number of bits of the waiting mask, both equal to the total number of first warps, and the bit values at the same bit position in the ready mask and the waiting mask correspond to the same first warp, or the corresponding relationship between each bit value in the ready mask, each bit value in the waiting mask and the first warp is determined in advance, based on which the first logical processing can obtain an accurate processing result.

[0086] In some alternative embodiments, the policy arbiter corresponding to the first scheduling policy is configured to perform the following processing: for any first warp, perform a first logical process on the ready mask and the wait mask of the first warp to obtain a first intermediate bit value corresponding to the first warp, where the first intermediate bit value is used to indicate whether there is a first warp that is in the ready state and entered the scheduling wait state earlier than the first warp; perform a second logical process on the first intermediate bit value and the ready mask to obtain a result bit value corresponding to the first warp, where the result bit value is used to indicate whether the first warp is in the ready state and is the first to enter the scheduling wait state.

[0087] That is to say, the process of determining whether the first warp is the second warp that matches the first scheduling policy based on the first intermediate bit value after obtaining the first intermediate bit value can be summarized as the second logical process.

[0088] In some alternative embodiments, the policy arbiter corresponding to the first scheduling policy is configured to perform the following processing: for any first warp, perform an AND operation on the ready mask and the wait mask of the first warp to obtain a first intermediate mask corresponding to the first warp; for any first intermediate mask, perform an OR operation on multiple bit values of the first intermediate mask to obtain a first intermediate bit value corresponding to the first warp; perform a negation operation on each first intermediate bit value to obtain a second intermediate bit value corresponding to each first warp; based on the second intermediate bit values corresponding to multiple first warps, obtain a second intermediate mask; perform an AND operation on the second intermediate mask and the ready mask to obtain an arbitration mask, where the arbitration mask includes result bit values corresponding to each first warp. Here, the bit values at the same bit position in the ready mask and the wait mask correspond to the same first warp.

[0089] In some alternative embodiments, the arbitration result includes the arbitration mask.

[0090] In some alternative embodiments, the ready state and the state of having entered the scheduling wait state are represented based on a first preset bit value, and the unready state and the state of not having entered the scheduling wait state are represented based on a second preset bit value.

[0091] For any one first warp, when the value of the result bit value corresponding to the first warp is the first preset bit value, it indicates that there is no first warp that is in the ready state and entered the scheduling wait state earlier than the first warp, and the first warp is in the ready state; when the value of the result bit value corresponding to the first warp is the second preset bit value, it indicates that there is a first warp that is in the ready state and entered the scheduling wait state earlier than the first warp, or there is no first warp that is in the ready state and entered the scheduling wait state earlier than the first warp, but the first warp itself is in the unready state.

[0092] Correspondingly, in some alternative embodiments, a policy arbiter corresponding to the first scheduling policy is configured to determine a first warp with the result bit value being a first preset bit value as a second warp that matches the first scheduling policy. Correspondingly, if the result bit value is a second preset bit value, the first warp corresponding to the result bit value is not a second warp that matches the first scheduling policy.

[0093] It should be noted that based on the above implementation, the first scheduling policy can select a second warp after approximately four levels of logic (AND, OR, NOT, AND), and its selection logic is equivalent to that of the second scheduling policy based on polling. Therefore, the scheduling circuit does not introduce excessive timing overhead due to supporting another scheduling policy.

[0094] Figure 5 FIG. is a schematic diagram of an execution process of a first scheduling policy provided by an embodiment of the present disclosure. Refer to Figure 5 , there are N first warps to be scheduled, which are W(0), W(1), W(2),..., W(N - 2), W(N - 1) respectively. Among them, W(0) corresponds to a first bit value b1(0), which is used to indicate whether W(0) is in a ready state or an unready state; similarly, W(1) corresponds to a first bit value b1(1), W(2) corresponds to a first bit value b1(2),..., W(N - 2) corresponds to a first bit value b1(N - 2), and W(N - 1) corresponds to a first bit value b1(N - 1). Moreover, the above N first bit values can form a ready mask including N bit positions, that is, ready mask = b1(N - 1)b1(N - 2)...b1(2)b1(1)b1(0).

[0095] Further, for each first thread bundle, there is also a corresponding waiting mask, i.e., age mask. That is, the waiting mask corresponding to W(0) is age mask(0), and age mask(0) includes N second bit values corresponding one-to-one to N first thread bundles. Each second bit value is used to indicate whether the corresponding first thread bundle is in a scheduling waiting state prior to the current thread bundle. age mask(0) = b2_0(N - 1)b2_0(N - 2)…b2_0(2)b2_0(1)b2_0(0), where b2_0(N - 1) indicates whether W(N - 1) is in a scheduling waiting state prior to W(0), b2_0(N - 2) indicates whether W(N - 2) is in a scheduling waiting state prior to W(0), …, b2_0(2) indicates whether W(2) is in a scheduling waiting state prior to W(0), b2_0(1) indicates whether W(1) is in a scheduling waiting state prior to W(0), and the value of b2_0(0) is determined to be a preset value. Among them, the preset value can be "0", and "0" is also used to indicate that the first thread bundle corresponding to the second bit value is not in a scheduling waiting state prior to the current thread bundle. Similarly, the waiting mask corresponding to W(1) is age mask(1), the waiting mask corresponding to W(2) is age mask(2), …, the waiting mask corresponding to W(N - 2) is age mask(N - 2), and the waiting mask corresponding to W(N - 1) is age mask(N - 1).

[0096] As Figure 5 shown, for W(0), first perform a bitwise AND operation (&) on the ready mask and age mask(0) to obtain a first intermediate mask fir_IM mask with N bits (not shown in the figure). For example, for W(0), its corresponding first intermediate mask fir_IM mask(0) = b3_0(N - 1)b3_0(N - 2)…b3_0(2)b3_0(1)b3_0(0) = [b1(N - 1)&b2_0(N - 1)][b1(N - 2)&b2_0(N - 2)]…[b1(2)&b2_0(2)][b1(1)&b2_0(1)][b1(0)&b2_0(0)], where "&" represents an AND operation. Similarly, the first intermediate mask corresponding to each first thread bundle can be obtained.

[0097] Further, after obtaining the first intermediate mask of the first thread bundle, by performing an OR operation on the N bit values of the first intermediate mask, the first intermediate bit value corresponding to the first thread bundle can be obtained. For example, for W(0), its corresponding first intermediate bit value b_fir_IM(0) = b3_0(N - 1)|b3_0(N - 2)|…|b3_0(2)|b3_0(1)|b3_0(0), where "|" represents an OR operation or OR arithmetic. Similarly, the first intermediate bit value corresponding to each first thread bundle can be obtained.

[0098] On this basis, for each first thread bundle, by performing a negation operation on the first intermediate bit value corresponding to the first thread bundle, the second intermediate bit value corresponding to the first thread bundle can be obtained. For example, for W(0), its corresponding second intermediate bit value b_sec_IM(0) = b_fir_IM(0), where " " represents a negation operation or negation arithmetic. Similarly, the second intermediate bit value b_sec_IM(1) corresponding to W(1), the second intermediate bit value b_sec_IM(2) corresponding to W(2), ……, the second intermediate bit value b_sec_IM(N - 2) corresponding to W(N - 2), and the second intermediate bit value b_sec_IM(N - 1) corresponding to W(N - 1) can be obtained. As Figure 5 shown, combining the aforementioned OR operation "|" and the negation operation " " is represented as " |", which means that for any first thread bundle, after performing a bitwise OR operation on the first intermediate mask obtained according to the ready mask and the corresponding wait mask to obtain the first intermediate bit value, then performing a negation operation on the first intermediate bit value to obtain the second intermediate bit value.

[0099] Moreover, by combining the second intermediate bit values corresponding to multiple first thread bundles, the second intermediate mask sec_IM mask can be obtained, and the sec_IM mask = b_sec_IM(N - 1)b_sec_IM(N - 2)…b_sec_IM(2)b_sec_IM(1)b_sec_IM(0).

[0100] On this basis, perform a bitwise AND operation (&) on the sec_IM mask and the ready mask to obtain an arbitration mask rto mask consisting of N bits, rto mask = b4(N - 1)b4(N - 2)…b4(2)b4(1)b4(0), where each bit value is the result bit value of the corresponding first warp, and b4(N - 1) = b_sec_IM(N - 1)&b1(N - 1), b4(N - 2) = b_sec_IM(N - 2)&b1(N - 2), ……, b4(2) = b_sec_IM(2)&b1(2), b4(1) = b_sec_IM(1)&b1(1), b4(0) = b_sec_IM(0)&b1(0).

[0101] Exemplarily, if there are 4 first warps W0, W1, W2, and W3, corresponding to the first bit values 1, 0, 1, 0 respectively ("1" indicates in the ready state, "0" indicates in the unready state), in the combination where W0 corresponds to the lowest bit and W3 corresponds to the highest bit (the corresponding relationship between the bits in other masks and the first warps remains the same), the corresponding ready mask can be obtained as 0101. Further, the waiting mask age mask(0) corresponding to W0 is 0000, the waiting mask age mask(1) corresponding to W1 is 0001, the waiting mask age mask(2) corresponding to W2 is 0011, and the waiting mask age mask(3) corresponding to W3 is 0111 ("1" indicates that the corresponding first warp enters the scheduling waiting state before the current warp, "0" indicates that the corresponding first warp does not enter the scheduling waiting state before the current warp).

[0102] First, for W0, calculate ready mask&age mask(0) = (0101)&(0000) = 0000, so as to obtain the first intermediate mask fir_IM mask(0) corresponding to W0 as 0000. Then perform an OR operation on the multiple bit values of fir_IM mask(0), that is, 0|0|0|0, to obtain the first intermediate bit value b_fir_IM(0) corresponding to W0 as 0; perform a negation operation on the first intermediate bit value b_fir_IM(0) to obtain the second intermediate bit value b_sec_IM(0) corresponding to W0 as 1.

[0103] Similarly, for W1, calculate ready mask & age mask(1) = (0101) & (0001) = 0001, so as to obtain the first intermediate mask fir_IM mask(1) corresponding to W1 as 0001. Then perform an OR operation on multiple bit values of fir_IM mask(1), that is, 0|0|0|1, to obtain the first intermediate bit value b_fir_IM(1) corresponding to W1 as 1; perform a negation operation on the first intermediate bit value b_fir_IM(1) to obtain the second intermediate bit value b_sec_IM(1) corresponding to W1 as 0.

[0104] For W2, calculate ready mask & age mask(2) = (0101) & (0011) = 0001, so as to obtain the first intermediate mask fir_IM mask(2) corresponding to W2 as 0001. Then perform an OR operation on multiple bit values of fir_IM mask(2), that is, 0|0|0|1, to obtain the first intermediate bit value b_fir_IM(2) corresponding to W2 as 1; perform a negation operation on the first intermediate bit value b_fir_IM(2) to obtain the second intermediate bit value b_sec_IM(2) corresponding to W2 as 0.

[0105] For W3, calculate ready mask & age mask(3) = (0101) & (0111) = 0101, so as to obtain the first intermediate mask fir_IM mask(3) corresponding to W3 as 0101. Then perform an OR operation on multiple bit values of fir_IM mask(3), that is, 0|1|0|1, to obtain the first intermediate bit value b_fir_IM(3) corresponding to W3 as 1; perform a negation operation on the first intermediate bit value b_fir_IM(3) to obtain the second intermediate bit value b_sec_IM(3) corresponding to W3 as 0.

[0106] On this basis, combine 4 second intermediate bit values to obtain the second intermediate mask sec_IMmask = 0001. Perform an AND operation on it with the ready mask ready mask to obtain rto mask = sec_IM mask & ready mask = (0001) & (0101) = 0001. In this arbitration mask, the result bit value corresponding to W0 is 1, and the result bit values corresponding to other first thread bundles are all 0. Therefore, it is determined that W0 is the second thread bundle that matches the first scheduling policy.

[0107] It should be noted that according to the ready mask, among the 4 first thread warps, only W0 and W2 are in the ready state, while W1 and W3 are both in the unready state. Therefore, the subsequent second thread warp must be selected from W0 and W2. Further, according to the wait masks of the respective first thread warps, W0 enters the scheduling wait state first, followed by W1, then W2, and finally W3. In summary, W0 is the first thread warp that is in the ready state and enters the scheduling wait state first. Therefore, W0 is the second thread warp that matches the first scheduling policy. The second thread warp that is filtered out through the above preset logic processing and matches the first scheduling policy is also W0. Therefore, the second thread warp that matches the first scheduling policy can be accurately filtered out from the first thread warps through the preset logic processing.

[0108] Exemplarily, if there are 4 first thread warps W0, W1, W2, and W3, corresponding to the first bit values 0, 0, 1, 1 respectively ("1" indicates being in the ready state, "0" indicates being in the unready state), with the combination method where W0 corresponds to the lowest bit and W3 corresponds to the highest bit (the corresponding relationship between the bit positions in other masks and the first thread warps remains the same), the corresponding ready mask can be obtained as 0011. Further, the wait mask age mask(0) corresponding to W0 is 0000, the wait mask age mask(1) corresponding to W1 is 0001, the wait mask age mask(2) corresponding to W2 is 0011, and the wait mask age mask(3) corresponding to W3 is 0111 ("1" indicates that the corresponding first thread warp enters the scheduling wait state earlier than the current thread warp, "0" indicates that the corresponding first thread warp does not enter the scheduling wait state earlier than the current thread warp).

[0109] First, for W0, calculate ready mask & age mask(0) = (1100) & (0000) = 0000, so as to obtain the first intermediate mask fir_IM mask(0) corresponding to W0 as 0000. Then, perform an OR operation on the multiple bit values of fir_IM mask(0), that is, 0|0|0|0, to obtain the first intermediate bit value b_fir_IM(0) corresponding to W0 as 0; perform a negation operation on the first intermediate bit value b_fir_IM(0) to obtain the second intermediate bit value b_sec_IM(0) corresponding to W0 as 1.

[0110] Similarly, for W1, calculate ready mask & age mask(1) = (1100) & (0001) = 0000, so as to obtain the first intermediate mask fir_IM mask(1) corresponding to W1 as 0000. Then perform an OR operation on multiple bit values of fir_IM mask(1), that is, 0|0|0|0, to obtain the first intermediate bit value b_fir_IM(1) corresponding to W1 as 0; perform a negation operation on the first intermediate bit value b_fir_IM(1) to obtain the second intermediate bit value b_sec_IM(1) corresponding to W1 as 1.

[0111] For W2, calculate ready mask & age mask(2) = (1100) & (0011) = 0000, so as to obtain the first intermediate mask fir_IM mask(2) corresponding to W2 as 0000. Then perform an OR operation on multiple bit values of fir_IM mask(2), that is, 0|0|0|0, to obtain the first intermediate bit value b_fir_IM(2) corresponding to W2 as 0; perform a negation operation on the first intermediate bit value b_fir_IM(2) to obtain the second intermediate bit value b_sec_IM(2) corresponding to W2 as 1.

[0112] For W3, calculate ready mask & age mask(3) = (1100) & (0111) = 0100, so as to obtain the first intermediate mask fir_IM mask(3) corresponding to W3 as 0100. Then perform an OR operation on multiple bit values of fir_IM mask(3), that is, 0|1|0|0, to obtain the first intermediate bit value b_fir_IM(3) corresponding to W3 as 1; perform a negation operation on the first intermediate bit value b_fir_IM(3) to obtain the second intermediate bit value b_sec_IM(3) corresponding to W3 as 0.

[0113] On this basis, combine the 4 second intermediate bit values to obtain the second intermediate mask sec_IMmask = 0111. Perform an AND operation on it with the ready mask ready mask to obtain rto mask = sec_IM mask & ready mask = (0111) & (1100) = 0100. In this arbitration mask, the result bit value corresponding to W2 is 1, and the result bit values corresponding to other first thread bundles are all 0. Therefore, it is determined that W2 is the second thread bundle that matches the first scheduling policy.

[0114] It should be noted that in the above example, for W0, although it is the first warp to enter the scheduling waiting state, since it is in the unready state, it can be excluded through the AND operation between the second intermediate mask and the ready mask and is not selected as the second warp that matches the first scheduling policy. W1 is similar to W0. Although it enters the scheduling waiting state before W2, since it is in the unready state, it is also excluded and not selected as the second warp that matches the first scheduling policy. For W3, although it is in the ready state, since it enters the scheduling waiting state later than W2, it is excluded during the AND operation based on the ready mask and the waiting mask. Finally, W2 is determined as the second warp that matches the first scheduling policy.

[0115] As mentioned above, for each policy arbiter, it can determine the second warp that matches its corresponding preset scheduling policy. Since there are multiple policy arbiters, multiple second warps can be obtained. For the multiple second warps, a selector needs to further select one of them as the target warp according to the control signal of the control register and issue the target warp to schedule the target warp to execute data processing. Among them, the output of the selector can be information such as the identifier or name of the target warp that can uniquely identify the target warp.

[0116] In some optional embodiments, the control signal is determined according to the program characteristics of the handlers corresponding to multiple first warps. Among them, the program characteristics can reflect some characteristic information during the program execution.

[0117] Exemplarily, the second scheduling policy based on polling can enable each first warp to obtain an even execution opportunity. Therefore, for a program with data locality among the first warps, the second scheduling policy is friendly to its performance. Based on this, for the case with the above program characteristics, the second warp corresponding to the second scheduling policy can be selected as the target warp by using the control signal.

[0118] Exemplarily, for a handler with locality within a first warp, the execution of other first warps may depend on the end of the current first warp. In this case, usually good results cannot be obtained if the second scheduling policy is adopted. Therefore, for the case with the above program characteristics, the second warp corresponding to the first scheduling policy can be selected as the target warp by using the control signal.

[0119] Exemplarily, for the first warp (i.e., the producer - type warp) responsible for generating data or performing production - related tasks (i.e., the producer - type), it usually needs to cooperate with other types of warps (e.g., the consumer - type warp) to complete the functions of the entire system, which may involve operations such as data synchronization and data sharing. If the second scheduling strategy is used for this type of handler, usually good results cannot be obtained. Therefore, for the situation with the above - mentioned program characteristics, the control signal can be used to select the second warp corresponding to the first scheduling strategy as the target warp.

[0120] Exemplarily, for a handler with a certain instruction pattern, due to its uniform randomness, the second scheduling strategy often fails to achieve a very good scheduling effect. Therefore, for this situation, the control signal can be used to select the second warp corresponding to the first scheduling strategy as the target warp.

[0121] In some alternative embodiments, a control software can be preset. This control software can, based on program characteristics, generate corresponding control signals by writing different values to the control register, so as to control the selector to output the second warp determined by the corresponding policy arbiter as the target warp based on this control signal.

[0122] For example, if the control software writes "1" to the control register, it means selecting the second warp determined by the policy arbiter corresponding to the first scheduling strategy as the target warp; if the control software writes "0" to the control register, it means selecting the second warp determined by the policy arbiter corresponding to the second scheduling strategy as the target warp.

[0123] In summary, the scheduling circuit provided by the embodiments of the present disclosure supports parallelly screening the second warps corresponding to each preset scheduling strategy from multiple first warps based on multiple preset scheduling strategies, and then further screening out the one that better matches the program characteristics from these second warps as the target warp, and then being able to schedule the target warp to execute the corresponding data processing. This scheduling circuit can combine the characteristics of different preset scheduling strategies, screen out a more suitable and matching target warp, optimize the scheduling scheme, and thus help improve the program execution performance.

[0124] The second aspect of the embodiments of the present disclosure provides a scheduling method.

[0125] Figure 6 It is a flowchart of a scheduling method provided by the embodiments of the present disclosure. Referring to Figure 6 This scheduling method may include the following steps.

[0126] Step S61: Select a second thread bundle that matches each preset scheduling policy from multiple first thread bundles according to the status information of the multiple first thread bundles. The number of preset scheduling policies is multiple and the multiple preset scheduling policies are different.

[0127] Step S62: Select a target thread bundle from the second thread bundles that match each preset scheduling policy according to the program characteristics of the handlers corresponding to the multiple first thread bundles, so as to schedule the target thread bundle to execute data processing.

[0128] In some alternative embodiments, the status information of the first thread bundle includes the ready status information and the waiting status information of the first thread bundle. The ready status information is used to indicate whether the first thread bundle is in a ready state or an unready state, and the waiting status information is used to indicate the order in which the first thread bundle enters the scheduling waiting state.

[0129] In some alternative embodiments, the preset scheduling policy includes a first scheduling policy. The first scheduling policy is used to use the first thread bundle that is in a ready state and is the first to be in the scheduling waiting state as the second thread bundle. Correspondingly, selecting a second thread bundle that matches each preset scheduling policy from multiple first thread bundles according to the status information of the multiple first thread bundles includes: selecting, from the multiple first thread bundles, the first thread bundle that is in a ready state and is the first to be in the scheduling waiting state as the second thread bundle that matches the first scheduling policy according to the ready status information and the waiting status information of the multiple first thread bundles.

[0130] Further, for the implementation process of selecting a second thread bundle that matches the preset scheduling policy from multiple first thread bundles based on the preset scheduling policy, and selecting a target thread bundle from multiple second thread bundles, reference may be made to the relevant content of the embodiments of the present disclosure, which will not be elaborated herein.

[0131] In the embodiments provided by the present disclosure, a second thread bundle that matches each preset scheduling policy is selected from multiple first thread bundles according to the status information of the multiple first thread bundles, and a target thread bundle is selected from the second thread bundles that match each preset scheduling policy according to the program characteristics of the handlers corresponding to the multiple first thread bundles, so as to schedule the target thread bundle to execute data processing. Since different preset scheduling policies are used in the process of thread bundle scheduling, therefore, a second thread bundle that matches each preset scheduling policy can be screened out from multiple first thread bundles, so that the multiple second thread bundles screened out incorporate the characteristics of different preset scheduling policies. On this basis, a target thread bundle that is more matched with the program characteristics can be further screened out from multiple second thread bundles according to the program characteristics, so as to be able to schedule the target thread bundle to execute the corresponding data processing, which helps to improve the program execution performance.

[0132] The third aspect of the embodiments of the present disclosure provides a scheduling unit.

[0133] Figure 7 It is a schematic diagram of a scheduling unit provided by the embodiments of the present disclosure. Refer to Figure 7 , the scheduling unit 700 includes a scheduling circuit 710 and a sending circuit 720.

[0134] Among them, the sending circuit 720 is used to send the target warp determined by the scheduling circuit 710 to a preset processor, and the scheduling circuit 710 adopts the scheduling circuit described in any one of the embodiments of the present disclosure.

[0135] In the embodiments provided by the present disclosure, the scheduling unit includes a scheduling circuit and a sending circuit. Among them, corresponding policy arbitrators are configured in the scheduling circuit for different preset scheduling policies, so that the second warps matching each preset scheduling policy (or policy arbitrator) can be screened out from multiple first warps in parallel, so that the characteristics of different preset scheduling policies are aggregated in the screened multiple second warps. On this basis, the control signal of the control register can be determined according to the program characteristics of the processing programs corresponding to the multiple first warps, so that the target warp that better matches the program characteristics can be further screened out from the multiple second warps, improving the scheduling effect, and further improving the program execution performance.

[0136] The fourth aspect of the embodiments of the present disclosure provides a processing system.

[0137] Figure 8 It is a schematic diagram of a processing system provided by the embodiments of the present disclosure. Refer to Figure 8 , the processing system 800 includes at least one scheduling unit 810 and at least one processing unit 820.

[0138] Among them, the processing unit 820 is used to perform data processing according to the target warp, and the scheduling unit 810 adopts the scheduling unit described in any one of the embodiments of the present disclosure.

[0139] In some alternative embodiments, the processing unit 820 may be a computing unit or a memory access unit, and the embodiments of the present disclosure do not limit this.

[0140] It should be noted that the above - mentioned processing system can be a processing system based on a Graphics Processing Unit (GPU), a processing system based on General - Purpose Computing on Graphics Processing Units (GPGPU), or a processing system based on a Neural - Network Processing Unit (NPU). The embodiments of the present disclosure do not limit this.

[0141] In the embodiments provided by the present disclosure, the scheduling unit in the processing system is configured with corresponding policy arbitrators for different preset scheduling policies, so as to be able to parallelly screen out second warps that match each preset scheduling policy (or policy arbitrator) from multiple first warps. As a result, the multiple second warps screened out incorporate the characteristics of different preset scheduling policies. On this basis, the control signals of the control registers can be determined according to the program characteristics of the processing programs corresponding to the multiple first warps. Then, the target warps that are more matched with the program characteristics can be further screened out from the multiple second warps by using the control signals, and the corresponding processing unit executes the corresponding data processing according to the target warps. In the above - mentioned processing process, since the second warps incorporate the characteristics of different preset scheduling policies and the target warps that are most matched with the program characteristics are further screened out from them, the scheduling effect can be improved, and thus the program execution performance can be enhanced.

[0142] It can be understood that, without violating the principle logic, the above - mentioned various embodiments of the present disclosure can be combined with each other to form combined embodiments. Due to space limitations, the present disclosure will not elaborate further. Those skilled in the art can understand that in the above - mentioned method of the specific implementation manner, the specific execution order of each step and the setting of the functional modules should be determined according to their functions and possible internal logics.

[0143] In addition, the present disclosure also provides an electronic device and a computer - readable storage medium.

[0144] Figure 9 It is a block diagram of an electronic device provided by an embodiment of the present disclosure.

[0145] Refer to Figure 9, an embodiment of the present disclosure provides an electronic device, which includes: at least one processor 901 connected by a bus, at least one memory 902, and one or more I / O interfaces 903; wherein, the memory 902 stores one or more computer programs executable by at least one processor 901, and the one or more computer programs are executed by at least one processor 901 so that at least one processor 901 can execute the scheduling method described in any one of the embodiments of the present disclosure.

[0146] Figure 10 It is a block diagram of an electronic device provided by an embodiment of the present disclosure.

[0147] Referring to Figure 10 , an embodiment of the present disclosure provides an electronic device, which includes a plurality of processing cores 1001 and a network-on-chip 1002. Among them, the plurality of processing cores 1001 are all connected to the network-on-chip 1002, and the network-on-chip 1002 is used for interacting data between the plurality of processing cores and external data.

[0148] Among them, one or more instructions are stored in one or more processing cores 1001, and the one or more instructions are executed by one or more processing cores 1001 so that one or more processing cores 1001 can execute the scheduling method described in any one of the embodiments of the present disclosure.

[0149] An embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored. Among them, the computer program implements the scheduling method described in any one of the embodiments of the present disclosure when executed by a processor / processing core. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0150] An embodiment of the present disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the scheduling method described in any one of the embodiments of the present disclosure.

[0151] Those of ordinary skill in the art will understand that all or some of the steps in the methods disclosed above, and the functional modules / units in systems and devices, can be implemented as software, firmware, hardware, and appropriate combinations thereof. In the hardware implementation, the division of functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be executed by several physical components in cooperation. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable storage medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media).

[0152] As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cassettes, tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically includes computer-readable program instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0153] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device through a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0154] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine - related instructions, microcode, firmware instructions, state - setting data, or source code or object code written in any combination of one or more programming languages, including object - oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer - readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand - alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, by using the state information of the computer - readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field - programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer - readable program instructions to implement various aspects of the present disclosure.

[0155] The computer program product described herein may be implemented specifically in the form of hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is specifically embodied as a computer storage medium. In another alternative embodiment, the computer program product is specifically embodied as a software product, such as a Software Development Kit (SDK), etc.

[0156] Aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and the combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer - readable program instructions.

[0157] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, when executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises a manufacture including instructions which implement various aspects of the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0158] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process, such that the instructions which execute on the computer, other programmable data processing apparatus, or other devices implement the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0159] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of code, or a portion of an instruction, which comprises one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two consecutive blocks may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by special-purpose hardware-based systems that perform the specified functions or acts, or combinations of special-purpose hardware and computer instructions.

[0160] Example embodiments have been disclosed herein, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, the features, characteristics, and / or elements described in connection with a particular embodiment may be used singly or in combination with other embodiments. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the present disclosure as set forth by the appended claims.

Claims

1. A scheduling circuit, characterized in that, Including: A plurality of policy arbitrators, control registers, and selectors, where different policy arbitrators correspond to different preset scheduling policies; Any one of the policy arbitrators is configured to select a second thread bundle that matches the preset scheduling policy of the policy arbitrator from a plurality of the first thread bundles according to the status information of the plurality of first thread bundles; The selector is configured to select a target thread bundle from a plurality of second thread bundles determined based on the plurality of policy arbitrators according to the control signal of the control register, so as to schedule the target thread bundle to execute data processing, and the control signal is determined according to the program characteristics of the processing programs corresponding to the plurality of first thread bundles.

2. The circuit according to claim 1, wherein The status information of the first thread bundle includes the ready status information and the waiting status information of the first thread bundle. The ready status information is used to indicate whether the first thread bundle is in a ready state or an unready state, and the waiting status information is used to indicate the order in which the first thread bundle enters the scheduling waiting state.

3. The circuit according to claim 2, wherein The preset scheduling policy at least includes a first scheduling policy, and the first scheduling policy is used to use the first thread bundle that is in a ready state and is the first to be in the scheduling waiting state as the second thread bundle; The policy arbitrator corresponding to the first scheduling policy is configured to select, from a plurality of the first thread bundles, the first thread bundle that is ready and is the first to be in the scheduling waiting state as the second thread bundle according to the ready status information and the waiting status information of the plurality of first thread bundles.

4. The circuit according to claim 3, wherein The ready status information is represented based on a ready mask, and the waiting status information is represented based on a waiting mask; Any one of the policy arbitrators is configured to select a second thread bundle that matches the preset scheduling policy of the policy arbitrator from a plurality of the first thread bundles according to the input ready masks and waiting masks of the plurality of first thread bundles, generate an arbitration result for indicating the second thread bundle, and send the arbitration result to the selector; The selector is configured to select the target thread bundle from a plurality of the second thread bundles based on the control signal according to the arbitration results of the plurality of policy arbitrators, and output a selection result for indicating that the target thread bundle is the launch thread bundle.

5. The circuit according to claim 4, wherein Further including: The ready mask corresponding to the first thread bundle includes a first bit value, and the first bit value is used to represent whether the corresponding first thread bundle is in a ready state or an unready state; The waiting mask corresponding to the first thread bundle includes a second bit value, and the second bit value is used to represent whether the first thread bundle corresponding to the second bit value enters the scheduling waiting state earlier than the current thread bundle.

6. The circuit according to claim 5, wherein The waiting mask is a mask generated according to the first thread bundles that enter the scheduling waiting state earlier than the current thread bundle when the current thread bundle first enters the scheduling waiting state.

7. The circuit according to claim 5, characterized in that, The policy arbitrator corresponding to the first scheduling policy is configured to perform preset logical processing on the ready mask and the waiting masks corresponding to each of the first thread bundles to obtain an arbitration result, and the arbitration result is used to indicate the second thread bundle that matches the first scheduling policy.

8. The circuit according to claim 7, wherein The policy arbitrator corresponding to the first scheduling policy is configured to perform the following processing: For any one of the first thread bundles, perform a first logical process on the ready mask and the wait mask of the first thread bundle to obtain a first intermediate bit value corresponding to the first thread bundle, where the first intermediate bit value is used to indicate whether there is a first thread bundle that is in the ready state and entered the scheduling wait state earlier than the first thread bundle; Perform a second logical process on the first intermediate bit value and the ready mask to obtain a result bit value corresponding to the first thread bundle, where the result bit value is used to indicate whether the first thread bundle is in the ready state and is the first to enter the scheduling wait state.

9. The circuit according to claim 8, wherein, The policy arbiter corresponding to the first scheduling policy is used to perform the following processes: For any one of the first thread bundles, perform an AND operation on the ready mask and the wait mask of the first thread bundle to obtain a first intermediate mask corresponding to the first thread bundle; For any one of the first intermediate masks, perform an OR operation on multiple bit values of the first intermediate mask to obtain a first intermediate bit value corresponding to the first thread bundle; Perform a negation operation on each of the first intermediate bit values to obtain a second intermediate bit value corresponding to each of the first thread bundles; Based on the second intermediate bit values corresponding to multiple first thread bundles, obtain a second intermediate mask; Perform an AND operation on the second intermediate mask and the ready mask to obtain an arbitration mask, where the arbitration mask includes result bit values corresponding to each of the first thread bundles; The arbitration result includes the arbitration mask.

10. The circuit according to claim 9, wherein The ready state and the state of having entered the scheduling wait state are represented based on a first preset bit value, and the not-ready state and the state of not having entered the scheduling wait state are represented based on a second preset bit value; For any one first thread bundle, when the value of the result bit value corresponding to the first thread bundle is the first preset bit value, it indicates that there is no first thread bundle that is in the scheduling wait state and ready earlier than the first thread bundle, and the first thread bundle is in the ready state; when the value of the result bit value corresponding to the first thread bundle is the second preset bit value, it indicates that there is a first thread bundle that is in the scheduling wait state and ready earlier than the first thread bundle, or there is no first thread bundle that is in the scheduling wait state and ready earlier than the first thread bundle, but the first thread bundle is in the not-ready state.

11. The circuit according to claim 10, characterized in that, The policy arbiter corresponding to the first scheduling policy is used to determine the first thread bundles with the value of the result bit value being the first preset bit value as the second thread bundles that match the first scheduling policy.

12. The circuit according to any one of claims 1 to 11, characterized in that, The preset scheduling policy further includes a second scheduling policy based on polling.

13. A scheduling method, characterized in that, It includes: According to the state information of multiple first thread bundles, select second thread bundles that match each preset scheduling policy from the multiple first thread bundles, where the number of preset scheduling policies is multiple and the multiple preset scheduling policies are different; According to the program characteristics of the handlers corresponding to the multiple first thread bundles, select a target thread bundle from the second thread bundles that match each preset scheduling policy to schedule the target thread bundle to perform data processing.

14. A scheduling unit, characterized in that, It includes: A scheduling circuit and a sending circuit; Wherein, the sending circuit is configured to send the target warp determined by the scheduling circuit to a preset processor, and the scheduling circuit adopts the scheduling circuit described in any one of claims 1 to 12.

15. A processing system, characterized in that, Comprising: At least one scheduling unit and at least one processing unit; Wherein, the processing unit is configured to perform data processing according to the target warp, and the scheduling unit adopts the scheduling unit described in claim 14.

16. An electronic device, characterized in that, Comprising: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor so that the at least one processor can execute the scheduling method described in claim 13.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program, when executed by a processor, implements the scheduling method described in claim 13.

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