Method and apparatus for manipulation of bit fields directly in a memory source

Abstract

A method and apparatus allowing for the direct manipulation of bit fields contained in a memory source. Logic circuitry performs a process wherein bit segments and bit fields contained in respective data strings are manipulated or moved along respective data strings, wherein the bit fields may not be aligned in accordance with data bytes contained in a respective data string. Additionally, the logic circuitry may mask any bits not associated with either the bit segment and the bit field in the respective data strings. The logic circuitry performs an arithmetic operation, wherein the masked respective data strings are arithmetically coupled to each other providing a resultant data string, the resultant data string containing the arithmetic result of the bit segment and the bit field segment as a bit field result. The logic circuitry can pass forward masks of the bit field result and any partially modified byte(s) instead of an entire mask of the respective data strings.

Description

1. Field of InventionThe present invention relates to the field of computer processors. More specifically, the invention relates to manipulation of bit fields by computer processors.2. Description of Related ArtIn typical computer systems, processors are utilized in order to perform specific operations on data, the data usually consisting of a large number of bits such as 64 bits, using a set of instructions that produce a desired result. For example, the processor may execute a subtraction instruction, wherein a first 64-bit value is subtracted from a second 64 bit value resulting in a third 64 bit value which can be stored to a memory or utilized for further calculations or instructions. However, with the advance in technology and utilization of multimedia applications, such as enhanced graphic displays, image processing, recognition algorithms and video compression / decompression, modern multimedia applications require the manipulation of large amounts of data which may be represe...

AI Technical Summary

Problems solved by technology

However, during transmission, errors may be introduced into the network data packet by, for example, interference or spurious network noise, resulting in the processing of an erroneous network data packet.

The processing of such an erroneous network data packet by the processor may result in the processor rejecting the network data packet, or even causing the processor itself to fail.

Some GPC architects have gone so far as to only support a single size of data items, thereby requiring the compiler to generate extra instructions when an inconvenient data size is needed for space reasons.

Similarly, due to the fact that the extra instructions require certain operations to be executed before processing the packet, the GPC processor speed and efficiency is further reduced.

First, the programmer has a much easier time in writing the code which manipulates the packet data.

As a result, the programmer (and compiler) need not understand the intricate details of a large number of different instructions in order to produce good code.

Images