102 results about "Power dissipation minimization" patented technology

A system and method is disclosed for minimizing power consumption of a sensor unit that is capable of detecting an object. Main circuitry operates the sensor unit in a high power mode of operation when the sensor unit detects an object. Low power control circuitry operates the sensor unit in a low power mode of operation when the sensor unit does not detect an object within a pre-determined period of time. The low power control circuitry also comprises a counter to periodically determine when to restore the sensor unit to a high power mode of operation. One advantageous embodiment of the sensor unit is a fingerprint sensor unit for detecting a finger to obtain fingerprint information.

The invention is directed towards minimizing power consumption in computer systems. One embodiment of the invention is a power management system that is used for a computer system that has at least one device and one power domain. This embodiment uses two different power managers to manage the power consumption of the device and the power domain. Specifically, this embodiment has (1) a first power manager that determines when to change power state of the device, and (2) a second power manager that determines when to change power state of the power domain. Each of these power managers decides to change the power state of its corresponding device or domain based on information from several different sources. These sources can include power-management clients and power managers of related domains or devices.

A method and a system of providing cellular/wireless network dual mode communication services are provided. The wireless network interface normally stays in the standby mode, and the cellular interface is closed. When receiving calls, the cellular system receives the calls and wakes up the wireless network system to communicate to the calls. Hence, the power consumption of the dual mode phone is minimized.

A non-volatile memory system includes a NAND flash memory device including a first flash translation layer that performs a garbage collection operation, and a host device including a file system and a second flash translation layer that controls an operation of the NAND flash memory device by interacting with the file system. Here, the host device provides application data in an in-ordered form to the NAND flash memory device. Thus, the non-volatile memory system can perform a random write operation at high speed, and can minimize power consumption due to unnecessary data transfer.

The invention relates to a MOS transistors substitutive circuit having a transformer/data interface function, in particular for ISDN networks, comprising first (11a) and second (11b) power supply/transmitter blocks, the first power supply/transmitter block (11a) being connected between a voltage reference (V) and a first data interface (RX), and the second power supply/transmitter block (11b) being connected between a ground potential reference (GND) and a second data interface (TX), both power supply/transmitter blocks being connected to a supply voltage reference (VDD). The MOS transistors substitutive circuit according to the invention comprises first (12) and second (12') MOS transistor pairs connected to the voltage reference (V), the MOS transistors being diode configured and held in their saturation range, so as to have a high A.C. impedance and virtually zero D.C. impedance, thereby minimizing power dissipation through the substitutive circuit.The invention also concerns a control and driving switch configuration for a network termination of at least first (11) and second (11') MOS transistors substitutive circuits according to the invention, operating respectively in a first condition ("normal condition") of operation of the network termination characterized by the presence of the polarity reverse control signal (Scrp), and a second condition ("RM emergency condition") of operation of the network termination characterized by the absence of the polarity reverse control signal (Scrp). The control configuration selects the voltage reference being applied to the power supply/transmitter blocks.

Method and apparatus for finding an assignment of voltages to all power domains of an integrated circuit such that the power consumption of an integrated circuit design is minimized and timing requirements (signal propagation delay or slack) are met. This is done by modeling both internal and external signal paths in an integrated circuit which has a number of power domains. The relationship between slack and voltage for the external and internal signal propagation paths is modeled, typically as a linear approximation. The integrated circuit design is then abstracted to a simplified form in terms of power domain relations and a model is created and solved iteratively using, e.g., linear programming, of different voltage levels for each power domain and including the slack values and their relationship between the changes in voltage and slack, for both the internal and external paths.

An improved ultra-low power NVM module, which exhibits low power consumption and reduced layout area. An array of compact flash memory cells are programmed and erased in response to positive and negative boosted voltages. However, the compact flash memory cells are read using conventional supply voltages, thereby minimizing power consumption during a read operation. The ultra-low power NVM module of the present invention can be fabricated using conventional VLSI process steps. The ultra-low power NVM module of the present invention also allows simple operation in all modes (i.e., program, erase, read and standby).

A communications device for performing wireless communications includes: a data receiving section for receiving data by wireless communications; a data transmitting section for transmitting data by wireless communications; a mode switching section for switching an operation mode of the communications device between a first mode in which power is supplied to the data transmitting section, and a second mode in which power consumption in at least the data transmitting section is minimized over that in the first mode; and a determination section for determining whether the data receiving section has received designated data. The mode switching section switches the operation mode of the communications device from the second mode to the first mode if, in a state in which the communications device is in the second mode, the determination section has determined that the data receiving section has received the designated data.

A hybrid disk drive is utilized to achieve speed optimization and minimization of power consumption by installing a flash memory device in the hybrid disk drive and efficiently controlling data flow between the flash memory device and the disk drive. The hybrid disk drive includes a, volatile memory unit, a nonvolatile memory unit, a disk unit, a host interface and a buffer controller disposed between the volatile memory unit, the nonvolatile memory unit, the host interface and the disk unit. The disk unit stores data by magnetizing the surface of the disk. The host interface receives a read data command from the host and transmits the data stored in the volatile memory unit to the host. The buffer controller is configured to read the data from the nonvolatile memory unit if the data is not stored in the volatile memory unit when the read data command is received from the host interface. The buffer controller also controls the storing of the read data in the volatile memory unit if the data is stored in the nonvolatile memory unit. Alternatively, if the data is not stored in the nonvolatile memory unit, the controller reads the data from the disk unit and stories it in the volatile memory unit.

The present invention relates generally to a combined radar and laser detector that enables a driver to drive safely and, more particularly, to a combined radar and laser detector, in which a signal receiving module for receiving various kinds of signals including traffic information and an information display module for informing a driver of the signals are separated, the signal receiving module and information display module are constructed to communicate with each other using wireless communication, and the information display module is integrated with a Global Positioning System (GPS) receiver detecting GPS data related to the location and speed of a moving vehicle, so that the combined radar and laser detector can not only provide accurate traffic information to the driver, but also allow the installation thereof to be easy, the miniaturization thereof to be achieved, and power consumption to be minimized.

According to the present invention, there is discussed an organic light-emitting diode display device. More particularly, the present invention relates to an organic light-emitting diode display device for minimizing power consumption in a standby mode in which no images are displayed but not in a normal mode in which typical images are displayed, and a driving circuit and method thereof. An organic light-emitting diode according to an embodiment of the present invention may control a drain-source voltage (V_DS) of the drive transistor provided in the pixel, thereby having an effect of capable of minimizing power consumption when in a standby mode.

An apparatus and a method for controlling an operation of an information processing device using movement data of the information processing device or a peripheral device are provided. An operation configuration variable set value for performing a predetermined function of the information processing device is changed according to movement data of the information processing device or the peripheral device detected by a movement detecting unit. After that, a predetermined function provided by the information processing device is automatically enabled or disabled, so that power consumption of a battery is minimized and user convenience in using the information processing device is enhanced.

A battery charger for a portable electronic device includes a linear charger to generate a substantially constant current for charging the battery and a switching voltage regulator to convert power supplied by an external adapter to a supply voltage for the linear charger. A feedback circuit controls operation of the switching voltage regulator so that the voltage supplied to the linear charger is substantially equal to the combination of the battery voltage and the drain-to-source voltage of the linear charger. In this way, power dissipation by the linear charger is minimized without requiring the use of a high accuracy current limited adapter.

Disclosed are a sensor network for transmitting data and a data transmitting method thereof. The sensor network includes one or more sensor nodes for collecting target data and transmitting the collected target data at an allocated sub-time slot among sub-time slots constituting each time slot corresponding to the collected target data, and a gathering node for allocating for the sensor nodes a sub-time slot for each of the time slots, and receiving the collected target data transmitted by the sensor nodes. Data transmission by bits reduces power consumption and does not require additional information transmission to prevent data collision. Therefore, power consumption is minimized and a plurality of sensor nodes possibly transmit data at one time, accordingly shortening transmission time.

In a processor system for audio processing, such as voice recognition and text-to-speech, a dedicated front-end processor, a core processor and a dedicated back-end processor are provided which are coupled by dual access stack. When an analog audio signal is inputted core processor is invoked only when a certain amount of data is present in the dual access stack. Likewise the back-end processor is invoked only when a certain amount of data is present in the dual access stack. This way the overall processing power required by the processing task is minimized as well as the power consumption of the processor system.