168 results about "Manycore processor" patented technology

The invention discloses a method and a device for realizing task splitting based on a multi-core processor and a related product. A device may be included as a processing device in a combined processing device, which may further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete computing operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is connected with the computing device and the processing device and used for storing data of the computing device and the processing device. The scheme disclosed by the invention provides a method for scheduling group matrix multiplication class operation task splitting on the multi-core processor, which can effectively reduce data memory access and improve processing efficiency.

The embodiment of the invention provides a starting method, a mirror image package used in the method comprises a mirror image combination mode and a plurality of system mirror images, and the mirror image combination mode is used for describing the relation among the system mirror images and the mapping relation between the system mirror images and processor cores. The mirror image package is packaged based on the first configuration information and the plurality of system mirror images, so that the plurality of system mirror images can be developed in parallel in the compiling process of the mirror image package, and the system mirror images do not need to be bound with the processor core during development; according to the method, the relationship among the plurality of system mirror images and the mapping relationship between the system mirror images and the processor core are defined through the first configuration information for describing the mirror image combination modes in the packaging process, so that the generation requirements of mirror image packets of different types of mirror image combination modes are met; if the mapping relation between the processor core and the system mirror image needs to be changed, only the first configuration information needs to be modified, the system mirror image does not need to be developed again, and the mirror image deployment convenience of the multi-core processor is improved.

The invention relates to a heterogeneous redundancy control method suitable for a multi-core embedded processor. The invention relates to the technical field of fault tolerance of embedded multi-core processors, in particular to a core-level redundancy method of a multi-core processor based on an asymmetric multi-core technology, the AMP technology can provide good isolation for core-level redundancy, and the problem that software redundancy cannot deal with permanent faults is solved. Compared with module-level redundancy, the method has the advantages that a check point rollback recovery mode is adopted in response to transient faults, switching and check-in are not needed, and the probability of faults possibly caused in the switching process is reduced. According to the invention, multiple cores in the processor module are used as redundant bodies, so that the waste of hardware space resources is reduced to a great extent.

The embodiment of the invention provides a data processing method and device based on a multi-core processor, equipment and a medium. The design of a directory, an address table item, a transaction table item and a data table item is introduced in the process of processing a request message initiated by any core of the multi-core processor; the efficiency of processing the request message and the related affairs and maintaining the cache consistency among the plurality of cores is effectively improved, and the cost and the overhead of maintaining the cache consistency are reduced.

A system for managing cache coherency comprises memory areas, processing cores, cache nodes each associated with at least one of the processing cores, and a hardware processor configured to: for each of the memory areas: cluster the processing cores into clusters according to memory access metrics in relation to the memory area; and for each of the clusters, associate the memory area with a caching scheme; and configure the processing cores to: receive from a first core a memory access command comprising a memory address associated with a memory area, where the first core is a member of a first cluster for the memory area; compute a determination of a target cache node according to the memory access command, where the target cache node is associated with a second core; and access the memory area according to the caching scheme associated with the memory area for the first cluster.

The invention provides a method for verifying cache consistency of a multi-core processor, electronic equipment and a storage medium, and the method comprises the steps: generating a model compiled by a target language according to an obtained first conversion rule between any two states of a cache line of the multi-core processor, analyzing the model, and verifying the cache consistency of the multi-core processor; therefore, at least one path of state transition of the cache line is obtained. By generating the excitation corresponding to the at least one path, the excitation is compiled into an executable file, so that the cache consistency of the multi-core processor is verified by running the executable file. Therefore, the generated model written by the target language can automatically generate the incentives for verifying the cache consistency, so that more incentives can be generated, more test scenes can be covered as much as possible, and the cache consistency verification of the multi-core processor is more comprehensive.

The invention discloses a privacy protection neural network reasoning method based on multi-point evaluation. According to the method, in the reasoning process of the privacy protection neural network, a given nonlinear function is constructed into a K-segment k-degree polynomial, a safe multiplication tree and a safe remainder tree are established, and then the remainder polynomial is safely evaluated. Due to the fact that the polynomial power needing to be evaluated in the online stage is reduced, the number of self-multiplication terms is reduced, the number of communication rounds of overall polynomial evaluation is reduced, the number of calling times of a secure multiplication triple in secret sharing is reduced, and the overhead of offline pre-calculation is correspondingly reduced. In addition, the hierarchical structure of the secure multiplication tree and the remainder tree supports multi-point input parallel computing, and the parallel computing capability of a modern multi-core processor or a GPU can be fully utilized.

The invention discloses a reinforcement learning-based multi-core processor task scheduling method under an NUMA architecture, and the method comprises the steps: carrying out the modeling of a task inputted into user equipment through a directed acyclic graph, and obtaining a task model; according to the NUMA architecture of the user equipment, constructing a processor resource model and a task scheduling model of the user equipment; constructing a task scheduling decision optimization problem into a Markov decision process model according to the task model, the processor resource model and the task scheduling model, modeling a state space, an action space and a reward function in the Markov decision process model, and performing reinforcement learning algorithm model training; and obtaining Q values of different actions in the current state by using the trained reinforcement learning algorithm model, and selecting the action with the highest Q value as a task mobilization decision result. According to the method, the task execution time can be reduced as much as possible to meet the strict real-time requirement, the throughput of the system is improved, and processor resources are fully utilized.

The invention discloses a method and a device for optimizing read-write performance of a database, computer equipment and a storage medium, the method comprises the following steps: setting to use an atomic variable to replace a common variable, setting to use an atomic read operation to replace a LwLock read protection operation, and setting to use an atomic write operation to replace a LwLock write protection operation to obtain set content; and initializing a database according to the set content to obtain an atomic variable database. According to the method, under the multi-core processor environment, the lock-free characteristic enables different cores to independently and efficiently process data without waiting for release of a lock, the parallel computing capacity of the multi-core processor is fully utilized, efficient execution of database read-write operation on the multi-core processor is achieved, and the data processing efficiency is improved. The scheme can be applied to the business fields of financial science and technology business, medical health maintenance and the like.

Methods and systems related to the efficient execution of complex computations by a multicore processor and the movement of data among the various processing cores in the multicore processor are disclosed. A multicore processor includes a set of processing cores and associated sets of processing pipelines, core controllers, routers, and network interface units. The multicore processor also includes a computation layer, for conducting computations using the set of processing cores, with executable instructions for the set of processing pipelines which are executed by the set of core controllers. The multicore processor also includes a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for the set of routers and the set of network interface units. The multicore processor also includes a set of programmable controllers, with executable instructions for reformatting computational data from the computation layer for transmission through the network-on-chip layer.

The invention discloses a smart city data processing method based on Beidou positioning, which relates to the technical field of electric digital data processing, and comprises the following steps: collecting data from a Beidou positioning module and an auxiliary sensor, and preprocessing the collected data; and performing event detection on the preprocessed data, and executing intelligent response operation according to an event detection result. And performing data integrity verification and privacy protection based on a cryptographic algorithm on the data. A data processing task is divided into a plurality of sub-tasks, parallel processing is carried out on the sub-tasks at the same time on a multi-core processor or a distributed computing platform through a multi-thread scheduling algorithm, and processing resources are distributed to the sub-tasks according to a dynamic scheduling strategy. And performing time sequence analysis on the historical data and the real-time data, and constructing a prediction decision model. According to the method, on the basis of a traditional data processing technology, comprehensive analysis and prediction of various sensor data of a city are realized by introducing multi-model hybrid prediction, meta-model dynamic weight calculation and residual correction.

Disclosed in the present invention are an FPGA-based simulation method for a high-voltage direct-connected energy storage system, and an apparatus. A power unit of the high-voltage direct-connected energy storage system is divided into an H-bridge and an energy storage unit part, the H-bridge and a grid-side topology are placed in an FPGA for simulation, an energy storage battery branch part is placed in a CPU for simulation, and the FPGA and the CPU exchange submodule voltage and current information by means of a PCIE bus. The FPGA establishes a Thevenin model of a single high-voltage direct-connected energy storage system submodule, performs algebraic superposition by using the series relationship of submodules, and calculates a submodule capacitor voltage, a submodule terminal voltage, and a bridge arm voltage; an equivalent model and the grid-side topology run with a simulation step size of 1µs in an FPGA of a simulator; the energy storage battery branch runs in a CPU of the simulator, and the CPU supports a user-defined energy storage battery model; and the respective advantages of a real-time multi-core processor and an FPGA are fully combined, so that the high-voltage direct-connected energy storage system with any number of submodules can be precisely simulated with a simulation step size of 1µs in real time on the FPGA.

The invention relates to a state synchronization method and device of a multi-core processor, a chip and equipment. The method comprises the following steps: controlling a plurality of processing cores of the multi-core processor to execute incremental operation on a target counter through an atomic instruction, wherein the incremental operation is used for adding one to the counting number of the target counter; under the condition that the counting number of the target counter is equal to the number of the processing cores of the multi-core processor, the unified timeout time of timers of the multiple processing cores is determined according to the target counter; synchronously configuring and starting timers of a plurality of processing cores in the multi-core processor according to the unified timeout time; and under the condition that the timers of the plurality of processing cores are overtime, triggering the synchronous state switching of the plurality of processing cores. By adopting the method, the synchronization precision of the multi-core processor can be improved.

A system may include a plurality of processing cores including at least a first processing core and a second processing core, a shared memory communicatively coupled to and accessible by each of the plurality of processing cores, a global monitor communicatively coupled to each of the plurality of processing cores and configured to control exclusive accesses to memory by each of the plurality of processing cores, and a software architecture embodied in non-transitory computer-readable media and configured to, when read and executed by the multicore processor, partition a plurality of processing tasks between the first processing core and the second processing core.

The invention provides video processing equipment and a video processing method. The video processing device comprises a multi-core processor, a task scheduling module, a visual processing unit and a cooperative control module, and the multi-core processor is used for sending a task queue corresponding to a video stream to the task scheduling module; the task queue comprises a plurality of to-be-processed tasks and real-time levels corresponding to the tasks; the cooperative control module is used for monitoring the states of the visual processing unit and the multi-core processor to obtain state information and sending the state information to the task scheduling module; the task scheduling module is used for dynamically distributing each task to a target processing component corresponding to each task according to the real-time level and state information corresponding to each task, and each target processing component comprises a multi-core processor and a visual processing unit for processing; the target processing component is used for processing each task to obtain an output result corresponding to the video stream; and the multi-core processor is used for outputting an output result corresponding to the video stream.

A method for scheduling an artificial neural network includes: accessing a processor representation of a multicore processor comprising processor cores, direct memory access cores, and a cost model; and accessing a network structure defining a set of layers. The method also includes, for each layer in the set of layers: generating a graph based on the processor representation, the graph defining compute nodes, data transfer nodes, and edges representing dependencies between the compute nodes and the data transfer nodes; and generating a schedule for the layer based on the graph, the schedule assigning the compute nodes to the processor cores and assigning the data transfer nodes to the direct memory access cores. The method further includes aggregating the schedule for each layer in the set of layers to generate a complete schedule for the artificial neural network.

The invention relates to a layout file multi-thread reading method and device, equipment and a storage medium. The method comprises the following steps: the layout file comprises a plurality of records; partitioning the layout file based on record information to obtain a to-be-read block and putting the to-be-read block into a to-be-read queue, and obtaining a to-be-partitioned compressed block and putting the to-be-partitioned compressed block into a to-be-partitioned queue; when it is monitored that a to-be-partitioned compressed block exists in the to-be-partitioned queue and an allocatable idle thread exists, the allocation thread decompresses and partitions the to-be-partitioned compressed block; when it is monitored that a to-be-read block exists in the to-be-read queue and a distributable idle thread exists, the distributable thread reads the to-be-read block to obtain data of the to-be-read block; and post-processing the obtained data of all the blocks to be read to complete reading of the layout file. Through block processing and support of multi-thread parallel computing, the performance of a multi-core processor is fully utilized, and the reading speed of the layout file is greatly improved.

The invention discloses a high-speed data transmission system based on a three-dimensional network-on-chip, and relates to the technical field of data transmission. In order to solve the problems of high diagonal communication delay, unreasonable node layout and poor heat dissipation of a traditional three-dimensional network on chip, the adopted scheme comprises a short connection 3D ScMesh topology module which is used for shortening the distance between nodes and reducing the communication delay through horizontal diagonal short connection and TSV vertical cross-layer interconnection on the basis of a 3D Mesh structure and matching an adaptive router and static routing algorithm; the SA-GA hybrid optimization algorithm module is used for completing position planning of the data acquisition nodes and the storage nodes through cooperation of SA and GA and finally realizing resource allocation optimization; and the layered heat dissipation layout module is used for deploying the storage nodes in a heat dissipation dominant area based on a heat distribution model, and solving the problem of heat accumulation of 3D NoC stacking. The method is suitable for scenes with high requirements on data transmission rate, delay and heat dissipation performance, such as a multi-core processor and a large-scale system-on-chip.

The invention discloses a high-density storage server and an operation method thereof. The high-density storage server comprises a case, and the interior of the case comprises a front part and a rear part; the front part is provided with 12 hot-pluggable storage node modules, each storage node module comprises a storage control node plate and two 3.5-inch mechanical hard disks, the storage control node plate is integrated with a low-power-consumption multi-core ARM SoC processor, DDR memory particles and eMMC storage particles, and a 2.5 Gb Ethernet interface is expanded through a 2.5 Gb Ethernet card chip; the rear part is provided with two Ethernet switching modules, two power supply modules, two fan modules and one BMC management module; each storage node module is connected with two 3.5-inch mechanical hard disks through two SATA (Serial Advanced Technology Attachment) buses, and is connected with the Ethernet switching module through a 2.5 Gb Ethernet interface; through modular and distributed hardware architecture design, the storage density and the system reliability are remarkably improved, the power consumption and the maintenance cost of the whole machine are reduced, and meanwhile efficient storage and access of data are ensured.

Examples include techniques to reduce memory power consumption during a system idle state. Cores of a single socket multi-core processor may be mapped to different virtual non-uniform memory architecture (NUMA) nodes and a dynamic random access memory (DRAM) may be partitioned into multiple segments that are capable of having self-refresh operations separately deactivated or activated. Different segments from among the multiple segments of DRAM may be mapped to the virtual NUMA nodes to allow for a mechanism to cause memory requests for pinned or locked pages of data to be directed to a given virtual NUMA node.

Providing processor core fault recovery without requiring system resets in multicore processor-based devices is disclosed herein. In some aspects, a processor-based device provides a plurality of processor cores that comprise a first processor core and a second processor core, with the first processor core configured to operate as a bootstrap processor core (BSP). The first processor core is configured to receive an interrupt corresponding to a registered timer event from a timer peripheral circuit, and, responsive to receiving the interrupt, transmit an interprocess interrupt (IPI) to the second processor core. The first processor core then determines whether a status update was successfully received from the second processor core in response to the IPI. If not, the first processor core performs one or more migration operations on the second processor core, masks the second processor core as offline for scheduling purposes, and blocks the second processor core from further health monitoring.

To suppress current consumption of a processor from exceeding an upper limit when each of a plurality of cores variably controls a clock frequency and a power supply voltage.SOLUTION: In a processor comprising a plurality of cores including floating-point units, a frequency / voltage control unit provided corresponding to each core supplies the corresponding core with a clock having a variable frequency and a power-supply voltage having a variable voltage. An instruction issuance control unit provided in each core controls the issuance of floating-point operation instructions to the floating-point unit, and reduces the issuance frequency of floating-point operation instructions to the floating-point unit when the current frequency value is greater than a reference frequency value or when the current power-supply voltage value is greater than a reference power-supply voltage value. This makes it possible to prevent the current consumption of the processor from exceeding an upper limit.SELECTED DRAWING: Figure 2

The invention relates to a layout file parallel reading method, device and equipment and a readable storage medium. The method comprises the following steps: the layout file comprises a plurality of records; partitioning the layout file on the basis of recorded information to obtain to-be-read blocks, and putting the to-be-read blocks into a to-be-read queue; when it is monitored that a to-be-read block exists in the to-be-read queue and a distributable idle thread exists, the distributable thread reads the to-be-read block, and data of the to-be-read block is obtained; and post-processing the obtained data of all the blocks to be read to complete reading of the layout file. According to the method, the performance of a multi-core processor is fully utilized through blocking processing and supporting multi-thread parallel computing, the reading speed of layout files is greatly increased, and a more efficient solution is provided for file loading and operation in semiconductor design.

Methods and systems for a digital signal processor (DSP) to transmit data between a first central processing unit (CPU) core (a producing core) and a second CPU core (a consuming core). The first and second CPU cores are time-aligned, such that cycles of one or more frames of the first CPU core correlate to one or more cycles of the second CPU core. The first and second CPU cores are configured to access a shared memory, through which data can be written and / or read by the first and second CPU cores.

A system and method for optimizing intrachip communication using machine learning-based codebook refinement is presented. The system employs an on-chip machine learning model to continuously analyze data patterns and update a codebook used for data compression in intrachip communication. Key aspects may comprise real-time data collection, feature extraction, performance monitoring, and gradual codebook updates. The system adapts to evolving data patterns, improving compression efficiency over time. A fallback mechanism ensures system stability by reverting to a conservative codebook if performance degrades. Security measures, including cryptographic signatures for updates and anomaly detection, are integrated. The system optimizes power consumption by adjusting operations based on the chip's power state. This adaptive approach significantly enhances intrachip communication efficiency, potentially improving overall chip performance and energy efficiency. The system's design allows for efficient execution within the constraints of on-chip resources, making it suitable for implementation in various multi-core processor architectures.

The present invention relates to a multi-threaded reading method, device, equipment and storage medium for a layout file. The method comprises: the layout file comprises a plurality of records; based on the record information, the layout file is processed in blocks to obtain blocks to be read and put into a queue to be read, and compressed blocks to be divided and put into a queue to be divided; when it is detected that there are compressed blocks to be divided in the queue to be divided and there are idle threads to be allocated, the threads are allocated to decompress and divide the compressed blocks to be divided into blocks; when it is detected that there are blocks to be read in the queue to be read and there are idle threads to be allocated, the threads are allocated to read and process the blocks to be read to obtain the data of the blocks to be read; the data of all the blocks to be read are post-processed to complete the reading of the layout file. By performing block processing and supporting multi-threaded parallel computing, the performance of the multi-core processor is fully utilized, and the reading speed of the layout file is greatly improved.

Systems and methods related to networks of computational nodes such as cores in a multicore processor are disclosed herein. A disclosed method for executing a computation using a network of computational nodes includes assigning a component computation of the complex computation to a first computational node in the network of computational nodes. The first computational node includes a local memory. The local memory is reserved to be used for a cache by the computational node for executing the component computation. The disclosed method also includes reserving a remote memory on a second computational node in the network of computational nodes to be used for the cache by the computational node for executing the component computation.

The embodiment of the present application provides a business interaction system, method, storage medium, and electronic device, wherein the system includes: a basic input / output system, a baseboard management controller connected to the basic input / output system, the baseboard management controller adopts a multi-core processor; the first processing core in the multi-core processor runs a first operating system, the second processing core in the multi-core processor runs a second operating system, the first operating system allows startup according to a target startup speed, and the target startup speed is greater than a first threshold; the first business in the baseboard management controller runs in the first operating system; the first business is a business for interacting with the basic input / output system during the startup of the basic input / output system. Therefore, the problem that the startup speed of the BIOS is seriously slowed down because the startup speed of the BMC is slower than that of the BIOS and the startup of the BIOS needs to interact with the BMC can be solved.

This invention provides a motor controller and engineering machinery. The motor controller includes: a driver connected to a motor; and an MPU (Multi-Core Processor), the MPU including a multi-core processor. Each core of the multi-core processor communicates with each other via a communication link for data exchange. The multi-core processor is connected to the driver and is used to detect motor operating status information and control the motor based on the operating status information. This invention adopts a single-chip MPU multi-core processor design, which can realize the motor controller function with a single MPU, meeting the requirements of small size and compact design of the controller, reducing equipment cost, and conforming to the ISO 13849 functional safety PLD / CAT2 class architecture.

The invention provides a multi-core processor system upgrading method based on backup cache regions. The multi-core processor system upgrading method comprises the steps that an upgrading mark region and at least two backup program cache regions distributed for each processing core are arranged in a nonvolatile memory; an upgrading process is executed, and the upgrading process comprises the steps that an upgrading mark area is read to determine a current effective program cache area set; wherein one program cache region set comprises one backup program cache region corresponding to each processing core; receiving upgrading data, and writing the upgrading data into a corresponding backup program cache region in the current non-effective program cache region set; after writing of the upgrade data is completed, the upgrade mark area is updated, so that the program cache area set where the upgrade data is written becomes effective, and upgrade version switching is completed. According to the method provided by the invention, the upgrading process is ensured to be safe and reliable through a backup cache region and upgrading mark switching mechanism.