57 results about "Manycore processor" patented technology

Disclosed in the present invention are an FPGA-based simulation method for a high-voltage direct-connected energy storage system, and an apparatus. A power unit of the high-voltage direct-connected energy storage system is divided into an H-bridge and an energy storage unit part, the H-bridge and a grid-side topology are placed in an FPGA for simulation, an energy storage battery branch part is placed in a CPU for simulation, and the FPGA and the CPU exchange submodule voltage and current information by means of a PCIE bus. The FPGA establishes a Thevenin model of a single high-voltage direct-connected energy storage system submodule, performs algebraic superposition by using the series relationship of submodules, and calculates a submodule capacitor voltage, a submodule terminal voltage, and a bridge arm voltage; an equivalent model and the grid-side topology run with a simulation step size of 1µs in an FPGA of a simulator; the energy storage battery branch runs in a CPU of the simulator, and the CPU supports a user-defined energy storage battery model; and the respective advantages of a real-time multi-core processor and an FPGA are fully combined, so that the high-voltage direct-connected energy storage system with any number of submodules can be precisely simulated with a simulation step size of 1µs in real time on the FPGA.

The invention provides video processing equipment and a video processing method. The video processing device comprises a multi-core processor, a task scheduling module, a visual processing unit and a cooperative control module, and the multi-core processor is used for sending a task queue corresponding to a video stream to the task scheduling module; the task queue comprises a plurality of to-be-processed tasks and real-time levels corresponding to the tasks; the cooperative control module is used for monitoring the states of the visual processing unit and the multi-core processor to obtain state information and sending the state information to the task scheduling module; the task scheduling module is used for dynamically distributing each task to a target processing component corresponding to each task according to the real-time level and state information corresponding to each task, and each target processing component comprises a multi-core processor and a visual processing unit for processing; the target processing component is used for processing each task to obtain an output result corresponding to the video stream; and the multi-core processor is used for outputting an output result corresponding to the video stream.

The invention discloses a high-speed data transmission system based on a three-dimensional network-on-chip, and relates to the technical field of data transmission. In order to solve the problems of high diagonal communication delay, unreasonable node layout and poor heat dissipation of a traditional three-dimensional network on chip, the adopted scheme comprises a short connection 3D ScMesh topology module which is used for shortening the distance between nodes and reducing the communication delay through horizontal diagonal short connection and TSV vertical cross-layer interconnection on the basis of a 3D Mesh structure and matching an adaptive router and static routing algorithm; the SA-GA hybrid optimization algorithm module is used for completing position planning of the data acquisition nodes and the storage nodes through cooperation of SA and GA and finally realizing resource allocation optimization; and the layered heat dissipation layout module is used for deploying the storage nodes in a heat dissipation dominant area based on a heat distribution model, and solving the problem of heat accumulation of 3D NoC stacking. The method is suitable for scenes with high requirements on data transmission rate, delay and heat dissipation performance, such as a multi-core processor and a large-scale system-on-chip.

Providing processor core fault recovery without requiring system resets in multicore processor-based devices is disclosed herein. In some aspects, a processor-based device provides a plurality of processor cores that comprise a first processor core and a second processor core, with the first processor core configured to operate as a bootstrap processor core (BSP). The first processor core is configured to receive an interrupt corresponding to a registered timer event from a timer peripheral circuit, and, responsive to receiving the interrupt, transmit an interprocess interrupt (IPI) to the second processor core. The first processor core then determines whether a status update was successfully received from the second processor core in response to the IPI. If not, the first processor core performs one or more migration operations on the second processor core, masks the second processor core as offline for scheduling purposes, and blocks the second processor core from further health monitoring.

This invention provides a motor controller and engineering machinery. The motor controller includes: a driver connected to a motor; and an MPU (Multi-Core Processor), the MPU including a multi-core processor. Each core of the multi-core processor communicates with each other via a communication link for data exchange. The multi-core processor is connected to the driver and is used to detect motor operating status information and control the motor based on the operating status information. This invention adopts a single-chip MPU multi-core processor design, which can realize the motor controller function with a single MPU, meeting the requirements of small size and compact design of the controller, reducing equipment cost, and conforming to the ISO 13849 functional safety PLD / CAT2 class architecture.

The invention provides a multi-core processor system upgrading method based on backup cache regions. The multi-core processor system upgrading method comprises the steps that an upgrading mark region and at least two backup program cache regions distributed for each processing core are arranged in a nonvolatile memory; an upgrading process is executed, and the upgrading process comprises the steps that an upgrading mark area is read to determine a current effective program cache area set; wherein one program cache region set comprises one backup program cache region corresponding to each processing core; receiving upgrading data, and writing the upgrading data into a corresponding backup program cache region in the current non-effective program cache region set; after writing of the upgrade data is completed, the upgrade mark area is updated, so that the program cache area set where the upgrade data is written becomes effective, and upgrade version switching is completed. According to the method provided by the invention, the upgrading process is ensured to be safe and reliable through a backup cache region and upgrading mark switching mechanism.

The application discloses a privacy protection neural network inference method based on multi-point evaluation. K Segment k Polynomial, and a safe multiplication tree and a safe remainder tree are established, and then a remainder polynomial is safely evaluated. Since the polynomial power to be evaluated in the online stage is reduced, the number of self-multiplication items is reduced, thereby reducing the communication round number of overall polynomial evaluation, reducing the number of calls of the safe multiplication triplets in the secret sharing, and correspondingly reducing the offline pre-computation cost. In addition, the layered structure of the safe multiplication tree and the remainder tree supports parallel computation of multi-point input, and can fully utilize the parallel computation capacity of a modern multi-core processor or a GPU.

The application relates to the technical field of data compression storage, and provides a high-throughput genome sequencing quality score data parallel compression method.The method comprises the following steps: segmenting an original gene sequencing file; performing random sampling and k-mer analysis on the sampling data to obtain statistical characteristic information and establish a parallel sequence partition model for binary classification; splicing two partition files obtained through binary classification according to splicing parameters; predicting the to-be-compressed file through a multivariate linear regression analysis prediction method to obtain compression rate gain and establish a parallel four-level run prediction mapping model for data redundancy elimination; and performing context modeling on two redundancy-eliminated subfiles through a multi-core processor cluster, and performing cascade compression in combination with arithmetic coding to obtain a final compressed file.Under the premise of significantly reducing quality score data compression time and peak memory overhead, the application also improves the quality score data compression rate, reduces the size of to-be-compressed storage files, and saves the construction cost of basic storage facilities.

The invention provides a multi-interface parallel ultra-high-definition image real-time processing and control device and method, and belongs to the technical field of image processing, and the device comprises a calculation processing module, a video input interface module, a video output interface module, an industrial automation control interface module and a data storage module. The calculation processing module is connected with the video input interface module, the user control and state indication module, the video output interface module, the industrial automation control interface module and the data storage module; the calculation processing module comprises an FPGA (Field Programmable Gate Array) processing unit and is used for receiving and transmitting data through various interfaces, executing temperature control, receiving multiple paths of video streams, carrying out parallel pipeline processing, outputting a processing result in real time and controlling various automatic mobile platforms; and the video input interface module comprises four HDMI (High Definition Multimedia Interface) 2.0 input interfaces and four Ethernet input interfaces. According to the invention, multiple inputs are compatible, parallel decoding and multi-core processor cooperative processing are realized, and the processing performance is improved.

The invention provides a multi-core processor cache coherence communication system based on FreeRTOS, and relates to the field of computer embedded systems, and the system comprises an application layer which comprises a plurality of tasks and is used for completing cross-core data interaction; the cache consistency communication layer is in communication connection with the application layer and the kernel layer; the cache consistency communication layer comprises a shared memory management module, a cache synchronization strategy scheduling module and a communication component synchronization adaptation module; the shared memory management module is used for tracking the cache state of the shared memory; the cache synchronization strategy scheduling module is used for selecting an optimal cache synchronization strategy according to the task and is linked with the task scheduler; the communication component synchronization adaptation module is used for identifying a corresponding shared memory block; the kernel layer comprises a memory manager, a task scheduler and a communication component; the communication component comprises queues, semaphores and event groups. According to the scheme, the problem of cache inconsistency is solved, and the correctness of cross-core data is ensured.

The invention discloses a satellite-borne soft platform virtual multi-core processor task synchronization method, which belongs to the technical field of ground test virtual simulation, and comprises the following steps: determining a time reference of system operation; and each core performs task cycle scheduling by using a system running time reference. According to the method, the synchronization of the task level of the virtual multi-core processor of the satellite-borne soft platform is realized by determining the running time reference of the system and controlling the starting and periodic execution of the multi-core task.

The embodiment of the invention provides a storage medium access method and device, and the method comprises the steps that a first processor core determines N first access requests, the first access requests are access requests which are generated by the first processor core and are not executed, and the first access requests are used for requesting to access a storage area in a first access range of a storage medium; the first processor core determines a target access request from the N first access requests and executes the target access request, the target access request being a first access request independent of the second access request, the second access request is generated earlier than the depended first access request, and a second access range corresponding to the second access request is overlapped with a first access range corresponding to the depended first access request. The first processor core is any processor core in the multi-core processor, and the plurality of processor cores do not need to compete for an exclusive lock of a storage medium and can execute respective first access requests in parallel, so that the concurrency capability of the multi-core processor can be improved.

The invention discloses a target tracking method based on twin network lightweight deployment and a storage medium, and the method comprises the steps: cutting an image in an image data set into a template region image and a search region image; generating a template backbone network weight file, a search backbone network weight file and a cross-correlation tracking head network weight file through a twin convolutional neural network; performing quantitative perception training on the network model, and performing fine tuning on weight parameters of the three weight files to obtain a trained network model configured with a fine-tuned template backbone network weight file, a fine-tuned search backbone network weight file and a fine-tuned cross-correlation tracking head network weight file; and deploying the trained network model in a multi-core processor, finally inputting a target image into the trained network model, and reasoning and calculating a target position by the trained network model to realize target tracking. The balance between precision and speed in a target tracking algorithm is realized, and the speed of target tracking calculation is improved.

Providing processor core fault recovery without requiring system resets in multicore processor-based devices is disclosed herein. In some aspects, a processor-based device provides a plurality of processor cores that comprise a first processor core and a second processor core, with the first processor core configured to operate as a bootstrap processor core (BSP). The first processor core is configured to receive an interrupt corresponding to a registered timer event from a timer peripheral circuit, and, responsive to receiving the interrupt, transmit an interprocess interrupt (IPI) to the second processor core. The first processor core then determines whether a status update was successfully received from the second processor core in response to the IPI. If not, the first processor core performs one or more migration operations on the second processor core, masks the second processor core as offline for scheduling purposes, and blocks the second processor core from further health monitoring.

The application discloses a kind of dual-redundancy control method and related device based on high-performance multicore processor belongs to engine controller technical field, the system dual-redundancy controller includes main control unit and slave control unit, main control unit and slave control unit respectively include DSP and FPGA, between DSP and FPGA through EMIF bus connection, between core 0 through SRIO connection, between core 1 through UART connection, core 0 communication connection core 1;The FPGA of main control unit and slave control unit is connected corresponding core 1, the core 1 of main control unit is connected to the FPGA of slave control unit by STATE signal, and the core 1 of slave control unit is connected to the FPGA of main control unit by STATE signal;Between the core 1 and FPGA of main control unit and slave control unit, there are two connections, one is connected by DOG signal, and the other is connected by WORK signal.The application not only can solve the conventional switching problem by hot standby redundancy switching, but also solve the switching problem under the condition of processor crash and recovery.

The invention discloses a clock calibration method and device. The method comprises the following steps: respectively creating a first clock calibration task and a second clock calibration task; distributing the first clock calibration task to a target core in a multi-core processor of the base station equipment, and executing the first clock calibration task; and in response to a clock calibration request initiated by the cellular service of the base station equipment, switching the first clock calibration task to the second clock calibration task, and executing the second clock calibration task. According to the method and the device, the clock precision can be kept under the condition that the base station equipment does not run any cellular service, a processor core is not preempted to stabilize a communication system, and at least one periodic clock calibration task is run on the base station equipment, so that the clock precision of the base station equipment is improved, upper-layer service and clock calibration are decoupled, and the service performance of the base station equipment is improved. And the stability and reliability of the system are ensured.

Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.

The application provides a kind of high-reliability parallel running method of aerospace SPARC multi-core processor, and the multi-core processor chip includes at least two processor cores, and all processor cores of the multi-core processor chip are independently running and performing inter-core notification and synchronization;Multi-processor state register monitors the running state of processor core and activates multi-core running.The application independently deploys multiple software modules on multiple processor cores for parallel computing, breaking through the traditional aerospace single-core processor software design mode, so that the software can adapt to large-scale software, multi-module integration, high real-time and high reliability requirements.At the same time, the application expands the supporting technology related to aerospace multi-core processor, including multi-core loading, inter-core interrupt, peripheral management, data sharing area, inter-core dynamic monitoring, etc., which has great value for the development of comprehensive electronic, integrated control and health management aerospace software in the field of satellite payload software.

The application discloses a network communication method and device, electronic equipment and medium, and relates to the technical field of computers. The method is applied to a first core in a heterogeneous multi-core processor. The heterogeneous multi-core processor further comprises a network controller connected with the first core. The method comprises the following steps: in the case that the network controller receives first network data, the first network data is parsed to obtain a network port corresponding to the first network data; based on the network port, a target core corresponding to the first network data in the heterogeneous multi-core processor is determined; in the case that the target core is a second core, the first network data is stored in a preset shared memory corresponding to the second core, and a first interrupt signal is generated. Through the application, each core in the heterogeneous multi-core processor can communicate with the outside through one network controller.

The disclosure discloses a data processing method based on a multi-core processor, a multi-core processor, a chip and a board. The multi-core processor can be included in a combined processing device as a computing device, and the combined processing device can further include an interface device and other processing devices. The computing device interacts with the other processing devices to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected to the computing device and the other processing devices, respectively, for storing data of the computing device and the other processing devices. The scheme of the disclosure optimizes the sorting processing based on the multi-core processor, and improves the operation processing efficiency.

The invention provides a smart cloud platform management system and device for realizing low carbon and zero carbon peak, and relates to the field of energy management. The method comprises the steps that a key coupling device module processes real-time data streams in parallel through a multi-core processor, a dynamic behavior model is constructed for each type of key coupling devices, and a cooperative control strategy is generated. The physical network interconnection module constructs a multi-energy network model, establishes an energy conversion interface and generates network state data. The simulation deduction module predicts future power load and carbon emission through a machine learning algorithm, and generates a load prediction result and a carbon emission prediction result. The optimization scheduling module generates an optimization scheduling plan under the constraint of a preset budget through a multi-objective optimization algorithm, and generates a risk assessment report through Monte Carlo simulation. And the feedback module generates a verification result and feeds back the verification result to the optimal scheduling module to dynamically adjust the scheduling plan. The technical problem of lack of cooperation in isolated operation of various energy networks is solved.

The application discloses a kind of coroutine pool scheduling management method, system, device and storage medium.The method creates corresponding coroutine task according to the service demand of application program;Then, the coroutine pool of host thread is established and initialized;Subsequently, the host thread is controlled to obtain hosting core, to start the host thread;And the coroutine task in the host thread is executed by task scheduling function.The method generates corresponding coroutine task according to the service demand of application program, and allocates hosting core for host thread according to coroutine task, can effectively distinguish the demand of different data processing tasks, implement more targeted and more fine-grained coroutine scheduling and execution control, realize the isolation of host thread and non-host thread, implement differentiated scheduling control, for multi-core processor architecture, realize the global unified resource allocation management of multiple coroutine pool.The application can be widely applied in the field of communication technology.

The application discloses a layered dynamic coordination-based on-board interference avoidance method and device. The method divides the interference avoidance task into interference avoidance in a multi-core processor and interference avoidance between multi-core processors. For the interference avoidance between multi-core processors, a high-layer scheduling controller performs interference avoidance according to the user density of adjacent spatial resource division units between the multi-core processors; for the interference avoidance in the multi-core processor, a media access control layer in the multi-core processor at a bottom layer is internally provided with a scheduling advance amount of each thread, so that different time points of adjacent threads on a pipeline correspond to the same time point of scheduling, resource allocation is performed at the same time point, a subsequent thread perceives a scheduling result of a previous thread, and interference avoidance is performed. The application reduces the calculation complexity of a single decision point, meets the real-time requirement of on-board scheduling, and significantly improves scheduling flexibility and interference response speed.

The application relates to a power service management method, device and system. The method comprises the following steps: in response to a received current power service execution instruction, determining a matched target power service container from a pre-established container warehouse; the power service container is a running carrier of a corresponding power service application program; and according to a preset resource scheduling rule, allocating a processor core to the target power service container, wherein the resource scheduling rule is that according to a power service type and time correlation relationship between the target power service container and a power service container in a running state, a processor core allocated to the target power service container is determined in a preset multi-core processor, and the processor core is used for executing a power service application program packaged in the target power service container. Through the application, power service processing quality can be ensured while energy consumption is saved.

The application discloses a kind of master-slave architecture multicore parallel target identification system based on embedded platform, including embedded platform for target identification of built-in neural network, embedded platform includes multicore processor and shared memory, one of multicore processor is main processor, the rest is slave processor;Neural network includes several convolution layers;Each convolution layer includes several neural network units A for extracting image features;Neural network unit A is arranged in slave processor;Other neural network components except neural network unit A are arranged in main processor, and the task of neural network unit A of slave processor is distributed by main processor;Main processor is stored in shared memory after size transformation to image;Neural network unit A reads image from shared memory, and outputs image feature to shared memory;Main processor simultaneously reads multiple image features from shared memory and identifies target image.

A multi-core processor can include a plurality of cores including at least a first core and a second core, a shared peripheral including a plurality of interrupt register sets including at least a first interrupt register set dedicated to the first core and a second interrupt register set dedicated to the second core, and a plurality of communication bridges including at least a first bridge interfacing between the first core and the shared peripheral and at least a second bridge interfacing between the second core and the shared peripheral. The first core can be configured to program the first interrupt register set via the first bridge to configure the shared peripheral for access by the first core. The second core can be configured to program the second interrupt register set via the second bridge to configure the shared peripheral for access by the second core.

This invention provides a control method for a multi-core processor. The method includes: a master core monitoring a slave core in real time; when the slave core is in a cache coherence failure state, saving the slave core's execution information and sending a reset command to the slave core; the slave core responding to the reset command sent by the master core repairing its cache unit according to the standby command in the storage unit; and after the repair is completed, entering a sleep state; and the slave core responding to a wake-up command sent by the master core resuming execution of its original task based on the execution information in the wake-up command. This invention ensures the normal access and use of cached data resources by the slave core, improving processor operating efficiency. Furthermore, this solution eliminates the need to pre-define fallback paths to the Uncached area for various potential error scenarios, resulting in lower software development costs.

The invention provides a task scheduling method and device and electronic equipment. The method comprises the steps of obtaining load data of a plurality of processing cores of a multi-core processor and attribute information of a plurality of tasks to be processed; based on the attribute information of the multiple tasks, determining priorities of the multiple tasks, and constructing a dependency graph of the multiple tasks; and based on the load data of the plurality of processing cores, the priorities of the plurality of tasks and the dependency graph, obtaining a scheduling strategy of the plurality of tasks. According to the task scheduling method provided by the invention, the scheduling strategy of the multiple tasks is determined based on the multi-dimensional data, the resource utilization rate can be improved, and the task response delay can be reduced.

The invention relates to a standardized framework for vehicle management tasks. Embodiments include a method of managing execution of real-time tasks in a multi-core processor system. The method includes instantiating a plurality of task instances, each task instance associated with a task-specific configuration. The method further includes executing, by each task instance, one or more worker threads according to a predefined execution phase. The method further includes invoking a task profile callback associated with each task instance to record task-level performance data during execution, and invoking an intra-task profile callback associated with each worker thread to record intra-task performance data within each execution stage. The method also includes synchronizing, by a global configuration, the task-level performance data and the intra-task performance data to provide a unified profiling of task instances executed across the cores.

This invention relates to the field of intelligent scheduling technology for multi-core processors, specifically an intelligent task scheduling method for multi-core central processing units based on artificial intelligence. The method includes: real-time acquisition of a set of task characteristic parameters for tasks to be processed and a set of real-time running status parameters for each processor core. These parameters are input into a pre-trained initial task allocation decision network to obtain a preliminary task-processor core matching probability matrix. A historical scheduling log database is accessed, and the weights of successful scheduling patterns recorded therein are used to correct the preliminary matrix, generating an updated matching probability matrix. Based on the updated matrix, the preferred processor core is determined for each task, forming the final task scheduling execution instruction. This method realizes the transformation of scheduling strategies from static rules to dynamic intelligent learning. By combining real-time status analysis and historical experience feedback, it improves the rationality of task allocation, system resource utilization efficiency, and overall processing performance in a multi-core environment.