182 results about "Manycore processor" patented technology

Embodiments of an apparatus and methods for controlling power of a processor having a plurality of cores can independently control individual or selected cores and power supply circuits corresponding to the cores based on, for example, an operation state of the processor or a power mode. Embodiments of an apparatus for controlling power of a processor having a plurality of cores can include a plurality of power supply units each capable of independently supplying a supply power to a plurality of cores provided in one processor, a unit for checking at least one among a use state, a use amount and a power mode of each core and for turning on/off each checked core, and a unit that contacts with the unit for checking for controlling the power supply units in response to an on/off operation of each core.

The invention discloses a method of high-speed concurrent processing of user requests of a Key-Value database. The method of the high-speed concurrent processing of the user requests of the Key-Value database comprises the steps of (1) receiving the user requests, and sequentially adding the user requests into a request buffering queue; (2) initializing a key code classification queuing list, continuously popping the user requests out from the request buffering queue according to a first-in first-out order, sorting the user requests to different pending processing queues according to different key codes of the user requests, and adding a mapping relation between the key codes and the pending processing queues into the key code classification queuing list; and (3) initializing a request assembly, continuously popping the user requests out on the head portion of the pending processing queues to the request assembly, using worker threads with a preset number to carry out concurrent processing on the user requests in the request assembly, and returning processing results to users. The method of the high-speed concurrent processing of the user requests of the Key-Value database has the advantages of being high in concurrent processing fine grit, good in concurrent processing capacity, high in use ratio of hardware resources, balanced in load of all processor cores in a multi-core processor, and capable of ensuring sequence among read-write dependent requests.

The invention discloses a multicore processor. The multicore processor comprises a test access port controller and a debugging connector; the test access port controller is provided with an interface connected with a joint test action group (JTAG) simulator; the debugging connector is connected with test access ports of all the cores of the processor; all the test access ports are connected with the debugging connector in parallel; and the test access port controller is used for controlling the debugging connector to connect the cores of the processor to be tested to the simulator. In the processor with the structure, the designs of the standard JTAG port and the test access ports are not needed to be changed. The invention also discloses a system and a method for debugging the multicore processor.

The invention discloses a binding system and method of multiple network interfaces. A Linux operating system and a real-time operating system simultaneously operate based on a multi-core processor. The real-time operating system comprises a physical network interface drive module and a network interface binding processing module aiming at the plurality of network interfaces. The Linux operating system comprises a virtual network interface drive module and a user configuration management interface. The physical network interface drive module is responsible for managing and controlling the network interfaces and receiving and dispatching physical network data. The network interface binding processing module is responsible for obtaining a data package from the physical network interface drive module, processing the received data package according to rules in a data receiving and processing rule base and submitting the processed data package to the virtual network interface drive module at a receiving side. The network interface binding processing module is responsible for receiving data from the virtual network interface drive module, processing the received data package according to a data dispatching rule base and submitting the processed data package to the physical network interface drive module to conduct dispatch at a dispatch side.

The present invention relates to a multicore processor 1. In order to select one of the multiple cores 21, 22, 23 in such a processor, an execution time of tasks which are performed multiple times is determined Based on the determined execution time on the individual cores 21, 22, 23, an appropriate core 21, 22, 23 for further executions of a task is selected. Additionally, the present invention further provides a code generator and code generating method for providing appropriate machine code for a multicore processor 1.

An architecture for a load-balanced groups of multi-stage manycore processors shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing.

Invented hardware logic based methods and systems enable dynamically allocating and assigning an array of processing cores among instances of software programs, based on at least in part on indications of which instances of the programs are ready-to-execute, wherein such an indication for any given program instance is based at least in part on whether its fast-access memory contents are ready for it to execute without it needing at that time access to memories other than its fast-access memory. The invention also provides hardware logic based mechanisms for automating the updating of the fast-access memories for instances of the programs dynamically sharing the array of cores according to control by the program instances via their associated hardware device registers, including while a given program instance whose fast-access memory contents are being updated is not assigned for execution on any of the cores.

The invention relates to the field of data communication, in particular to an implementation method and device for a security gateway based on a stream strategy. The implementation method for the security gateway based on the stream strategy provided aims to solve the problem that in the prior art, the processing efficiency of data messages and the utilization ratio of the processor, in particular the multi-core processor are very low. The strategy is uniformly set for the data stream by combining address mask and port range according to quintuple. One-step stream strategy match is carried for a data message and associated security function module is invoked on demand according to the match result, therefore, the inquiry efficiency of the stream strategy is enhanced when multiple security function modules coexist. The invention is mainly applied to the field of data communication.

The present invention provides debugging in a multi-core architecture. A method of monitoring thread execution within a multi-core processor architecture comprising a plurality of interconnected processor units for processing threads, the method comprising: receiving a plurality of thread parameter indicators, the thread The parameter indicator represents one or more parameters related to the function and/or identity and/or execution location of one or more threads; comparing at least one of these thread parameter indicators with a first plurality of predetermined criteria, Each of the first plurality of predetermined criteria represents an indicator of interest; and generating an output based on thread parameter indicators identified as being of interest as a result of said comparing.

A test method for a master-slave concurrent system running on a multicore processor includes the steps of establishing a PFA, otherwise called probabilistic finite automata, or probabilistic finite state machine, for a given regular expression; generating test patterns by running the PFA; splitting and merging the test patterns to generate an interleaved test pattern; and performing test on the master-slave system according to the interleaved test pattern. In an embodiment, the method further includes a step of debugging failures of the multicore processor during testing.

The invention relates to an FPGA-based scalable multi-core processor verification platform. It is a hardware platform for verifying a large-scale multi-core processor architecture. It is composed of several self-made FPGA development boards. Each development board is composed of a core board and a base board. The core board is embedded with cycloneIIIFPGA. The base board Equipped with 4 LVDS interfaces, it can communicate with other development boards through this interface. The connected development board array is rich in resources and can carry out large-scale FPGA prototype verification.

Systems and methods for scheduling instructions for execution on a multi-core processor reorder the execution of different threads to ensure that instructions specified as having localized memory access behavior are executed over one or more sequential clock cycles to benefit from memory access locality. At compile time, code sequences including memory access instructions that may be localized are delineated into separate batches. A scheduling unit ensures that multiple parallel threads are processed over one or more sequential scheduling cycles to execute the batched instructions. The scheduling unit waits to schedule execution of instructions that are not included in the particular batch until execution of the batched instructions is done so that memory access locality is maintained for the particular batch. In between the separate batches, instructions that are not included in a batch are scheduled so that threads executing non-batched instructions are also processed and not starved.

Different cores of a multicore processor are used to provide diagnostics of sophisticated hardware without full redundancy by static assignment of the cores during individual cycles of the control program and comparison of the outputs. A method of automatically generating diverse programs for execution by these cores may modify one program to compile two different instructions without functionally changing that program through the use of DeMorgan equivalents and diverse compiler optimizations.

The invention provides a multicore processor-oriented internal memory management system. The system is characterized by dividing progress memory access behaviors into a static attribute and a dynamic attribute, wherein the static attribute is used for describing general internal memory demand behaviors (sing-page or burst-mode requests) represented by progresses; the dynamic attribute is used for describing the characteristics represented by the progresses for internal memory requirements in the life cycle active processes of the progresses; and on the basis of analysis carried out on the static attribute and the dynamic attribute, internal memory operation modules in and between the progresses are imported. The system can be used for effectively improving the system distribution efficiency and effectively reducing the competition of internal memory resource locks between multiple cores.

The invention relates to a method for executing computer usable program code or a program made up of program parts on a multi-core processor (1) with a multiplicity of execution units (21, 22, 23, 24), each of which comprises a local memory (201) and at least one processing unit (202) communicatively linked to the local memory, wherein each of the execution units (21, 22, 23, 24) is connected to a communications network (30) for data exchange. One or more program parts are stored in at least some of the local memories (201) of the majority of execution units (21, 22, 23, 24). Execution of a program part is performed by the processing unit (202) of the particular execution unit (21, 22, 23, 24) that has the program part stored in its local memory (201).

An architecture for a multi-stage manycore processor shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing.

The invention discloses a method for reducing the data transmission delay, which comprises the steps that network equipment acquires data packet characteristics of a data packet to be scheduled; the network equipment searches a processing core corresponding to the data packet characteristics of the data packet to be scheduled according to a preset corresponding relationship between the data packetcharacteristics and processing cores in a multi-core processor; and the network equipment processes the data packet according to the searched processing core. Therefore, the data packet can be effectively prevented from being processed by the same processing core. The corresponding processing core is selected for processing according to the data packet characteristics, so that the processing coreutilization rate of the multi-core processor is effectively improved, the data packet can respond more timely, and the data transmission and processing speed is improved.

A scheduling method of a system on chip including a multi-core processor includes receiving a schedule-requested task, converting a priority assigned to the schedule-requested task into a linear priority weight, selecting a plurality of candidate cores, to which the schedule-requested task will be assigned, from among cores of the multi-core processor, calculating a preemption compare index indicating a current load state of each of the plurality of candidate cores, comparing the linear priority weight with the preemption compare index of the each of the plurality of candidate cores to generate a comparison result, and assigning the schedule-requested task to one candidate core of the plurality of candidate cores depending on the comparison result.