91 results about "Manycore processor" patented technology

The invention relates to a heterogeneous redundancy control method suitable for a multi-core embedded processor. The invention relates to the technical field of fault tolerance of embedded multi-core processors, in particular to a core-level redundancy method of a multi-core processor based on an asymmetric multi-core technology, the AMP technology can provide good isolation for core-level redundancy, and the problem that software redundancy cannot deal with permanent faults is solved. Compared with module-level redundancy, the method has the advantages that a check point rollback recovery mode is adopted in response to transient faults, switching and check-in are not needed, and the probability of faults possibly caused in the switching process is reduced. According to the invention, multiple cores in the processor module are used as redundant bodies, so that the waste of hardware space resources is reduced to a great extent.

A system for managing cache coherency comprises memory areas, processing cores, cache nodes each associated with at least one of the processing cores, and a hardware processor configured to: for each of the memory areas: cluster the processing cores into clusters according to memory access metrics in relation to the memory area; and for each of the clusters, associate the memory area with a caching scheme; and configure the processing cores to: receive from a first core a memory access command comprising a memory address associated with a memory area, where the first core is a member of a first cluster for the memory area; compute a determination of a target cache node according to the memory access command, where the target cache node is associated with a second core; and access the memory area according to the caching scheme associated with the memory area for the first cluster.

The invention provides a method for verifying cache consistency of a multi-core processor, electronic equipment and a storage medium, and the method comprises the steps: generating a model compiled by a target language according to an obtained first conversion rule between any two states of a cache line of the multi-core processor, analyzing the model, and verifying the cache consistency of the multi-core processor; therefore, at least one path of state transition of the cache line is obtained. By generating the excitation corresponding to the at least one path, the excitation is compiled into an executable file, so that the cache consistency of the multi-core processor is verified by running the executable file. Therefore, the generated model written by the target language can automatically generate the incentives for verifying the cache consistency, so that more incentives can be generated, more test scenes can be covered as much as possible, and the cache consistency verification of the multi-core processor is more comprehensive.

The invention discloses a privacy protection neural network reasoning method based on multi-point evaluation. According to the method, in the reasoning process of the privacy protection neural network, a given nonlinear function is constructed into a K-segment k-degree polynomial, a safe multiplication tree and a safe remainder tree are established, and then the remainder polynomial is safely evaluated. Due to the fact that the polynomial power needing to be evaluated in the online stage is reduced, the number of self-multiplication terms is reduced, the number of communication rounds of overall polynomial evaluation is reduced, the number of calling times of a secure multiplication triple in secret sharing is reduced, and the overhead of offline pre-calculation is correspondingly reduced. In addition, the hierarchical structure of the secure multiplication tree and the remainder tree supports multi-point input parallel computing, and the parallel computing capability of a modern multi-core processor or a GPU can be fully utilized.

Disclosed in the present invention are an FPGA-based simulation method for a high-voltage direct-connected energy storage system, and an apparatus. A power unit of the high-voltage direct-connected energy storage system is divided into an H-bridge and an energy storage unit part, the H-bridge and a grid-side topology are placed in an FPGA for simulation, an energy storage battery branch part is placed in a CPU for simulation, and the FPGA and the CPU exchange submodule voltage and current information by means of a PCIE bus. The FPGA establishes a Thevenin model of a single high-voltage direct-connected energy storage system submodule, performs algebraic superposition by using the series relationship of submodules, and calculates a submodule capacitor voltage, a submodule terminal voltage, and a bridge arm voltage; an equivalent model and the grid-side topology run with a simulation step size of 1µs in an FPGA of a simulator; the energy storage battery branch runs in a CPU of the simulator, and the CPU supports a user-defined energy storage battery model; and the respective advantages of a real-time multi-core processor and an FPGA are fully combined, so that the high-voltage direct-connected energy storage system with any number of submodules can be precisely simulated with a simulation step size of 1µs in real time on the FPGA.

The invention relates to a state synchronization method and device of a multi-core processor, a chip and equipment. The method comprises the following steps: controlling a plurality of processing cores of the multi-core processor to execute incremental operation on a target counter through an atomic instruction, wherein the incremental operation is used for adding one to the counting number of the target counter; under the condition that the counting number of the target counter is equal to the number of the processing cores of the multi-core processor, the unified timeout time of timers of the multiple processing cores is determined according to the target counter; synchronously configuring and starting timers of a plurality of processing cores in the multi-core processor according to the unified timeout time; and under the condition that the timers of the plurality of processing cores are overtime, triggering the synchronous state switching of the plurality of processing cores. By adopting the method, the synchronization precision of the multi-core processor can be improved.

The invention provides video processing equipment and a video processing method. The video processing device comprises a multi-core processor, a task scheduling module, a visual processing unit and a cooperative control module, and the multi-core processor is used for sending a task queue corresponding to a video stream to the task scheduling module; the task queue comprises a plurality of to-be-processed tasks and real-time levels corresponding to the tasks; the cooperative control module is used for monitoring the states of the visual processing unit and the multi-core processor to obtain state information and sending the state information to the task scheduling module; the task scheduling module is used for dynamically distributing each task to a target processing component corresponding to each task according to the real-time level and state information corresponding to each task, and each target processing component comprises a multi-core processor and a visual processing unit for processing; the target processing component is used for processing each task to obtain an output result corresponding to the video stream; and the multi-core processor is used for outputting an output result corresponding to the video stream.

The invention discloses a high-speed data transmission system based on a three-dimensional network-on-chip, and relates to the technical field of data transmission. In order to solve the problems of high diagonal communication delay, unreasonable node layout and poor heat dissipation of a traditional three-dimensional network on chip, the adopted scheme comprises a short connection 3D ScMesh topology module which is used for shortening the distance between nodes and reducing the communication delay through horizontal diagonal short connection and TSV vertical cross-layer interconnection on the basis of a 3D Mesh structure and matching an adaptive router and static routing algorithm; the SA-GA hybrid optimization algorithm module is used for completing position planning of the data acquisition nodes and the storage nodes through cooperation of SA and GA and finally realizing resource allocation optimization; and the layered heat dissipation layout module is used for deploying the storage nodes in a heat dissipation dominant area based on a heat distribution model, and solving the problem of heat accumulation of 3D NoC stacking. The method is suitable for scenes with high requirements on data transmission rate, delay and heat dissipation performance, such as a multi-core processor and a large-scale system-on-chip.

Providing processor core fault recovery without requiring system resets in multicore processor-based devices is disclosed herein. In some aspects, a processor-based device provides a plurality of processor cores that comprise a first processor core and a second processor core, with the first processor core configured to operate as a bootstrap processor core (BSP). The first processor core is configured to receive an interrupt corresponding to a registered timer event from a timer peripheral circuit, and, responsive to receiving the interrupt, transmit an interprocess interrupt (IPI) to the second processor core. The first processor core then determines whether a status update was successfully received from the second processor core in response to the IPI. If not, the first processor core performs one or more migration operations on the second processor core, masks the second processor core as offline for scheduling purposes, and blocks the second processor core from further health monitoring.

To suppress current consumption of a processor from exceeding an upper limit when each of a plurality of cores variably controls a clock frequency and a power supply voltage.SOLUTION: In a processor comprising a plurality of cores including floating-point units, a frequency / voltage control unit provided corresponding to each core supplies the corresponding core with a clock having a variable frequency and a power-supply voltage having a variable voltage. An instruction issuance control unit provided in each core controls the issuance of floating-point operation instructions to the floating-point unit, and reduces the issuance frequency of floating-point operation instructions to the floating-point unit when the current frequency value is greater than a reference frequency value or when the current power-supply voltage value is greater than a reference power-supply voltage value. This makes it possible to prevent the current consumption of the processor from exceeding an upper limit.SELECTED DRAWING: Figure 2

The present invention relates to a multi-threaded reading method, device, equipment and storage medium for a layout file. The method comprises: the layout file comprises a plurality of records; based on the record information, the layout file is processed in blocks to obtain blocks to be read and put into a queue to be read, and compressed blocks to be divided and put into a queue to be divided; when it is detected that there are compressed blocks to be divided in the queue to be divided and there are idle threads to be allocated, the threads are allocated to decompress and divide the compressed blocks to be divided into blocks; when it is detected that there are blocks to be read in the queue to be read and there are idle threads to be allocated, the threads are allocated to read and process the blocks to be read to obtain the data of the blocks to be read; the data of all the blocks to be read are post-processed to complete the reading of the layout file. By performing block processing and supporting multi-threaded parallel computing, the performance of the multi-core processor is fully utilized, and the reading speed of the layout file is greatly improved.

This invention provides a motor controller and engineering machinery. The motor controller includes: a driver connected to a motor; and an MPU (Multi-Core Processor), the MPU including a multi-core processor. Each core of the multi-core processor communicates with each other via a communication link for data exchange. The multi-core processor is connected to the driver and is used to detect motor operating status information and control the motor based on the operating status information. This invention adopts a single-chip MPU multi-core processor design, which can realize the motor controller function with a single MPU, meeting the requirements of small size and compact design of the controller, reducing equipment cost, and conforming to the ISO 13849 functional safety PLD / CAT2 class architecture.

The invention provides a multi-core processor system upgrading method based on backup cache regions. The multi-core processor system upgrading method comprises the steps that an upgrading mark region and at least two backup program cache regions distributed for each processing core are arranged in a nonvolatile memory; an upgrading process is executed, and the upgrading process comprises the steps that an upgrading mark area is read to determine a current effective program cache area set; wherein one program cache region set comprises one backup program cache region corresponding to each processing core; receiving upgrading data, and writing the upgrading data into a corresponding backup program cache region in the current non-effective program cache region set; after writing of the upgrade data is completed, the upgrade mark area is updated, so that the program cache area set where the upgrade data is written becomes effective, and upgrade version switching is completed. According to the method provided by the invention, the upgrading process is ensured to be safe and reliable through a backup cache region and upgrading mark switching mechanism.

The application discloses a privacy protection neural network inference method based on multi-point evaluation. K Segment k Polynomial, and a safe multiplication tree and a safe remainder tree are established, and then a remainder polynomial is safely evaluated. Since the polynomial power to be evaluated in the online stage is reduced, the number of self-multiplication items is reduced, thereby reducing the communication round number of overall polynomial evaluation, reducing the number of calls of the safe multiplication triplets in the secret sharing, and correspondingly reducing the offline pre-computation cost. In addition, the layered structure of the safe multiplication tree and the remainder tree supports parallel computation of multi-point input, and can fully utilize the parallel computation capacity of a modern multi-core processor or a GPU.

The application relates to the technical field of data compression storage, and provides a high-throughput genome sequencing quality score data parallel compression method.The method comprises the following steps: segmenting an original gene sequencing file; performing random sampling and k-mer analysis on the sampling data to obtain statistical characteristic information and establish a parallel sequence partition model for binary classification; splicing two partition files obtained through binary classification according to splicing parameters; predicting the to-be-compressed file through a multivariate linear regression analysis prediction method to obtain compression rate gain and establish a parallel four-level run prediction mapping model for data redundancy elimination; and performing context modeling on two redundancy-eliminated subfiles through a multi-core processor cluster, and performing cascade compression in combination with arithmetic coding to obtain a final compressed file.Under the premise of significantly reducing quality score data compression time and peak memory overhead, the application also improves the quality score data compression rate, reduces the size of to-be-compressed storage files, and saves the construction cost of basic storage facilities.

The invention provides a closed-loop watchdog security enhancement method and device, equipment and a storage medium, and relates to the technical field of computers. A closed-loop watchdog security enhancement method is applied to a multi-core processor system, and comprises the following steps: in response to a situation that any processor in the multi-core processor system successfully completes a watchdog feeding operation, sending a monitoring signal to an adjacent next processor based on the processor; a plurality of processors in the multi-core processor system are configured to be a closed-loop structure for sequentially transmitting monitoring signals; in response to the situation that each processor does not receive a monitoring signal sent by an adjacent previous processor within the target timeout time, determining that the previous processor is an abnormal processor; and reading the abnormal information of the abnormal processor, and sending the abnormal information to the cloud platform. Therefore, the coverage rate and the sensitivity of fault detection are improved.

The invention provides a multi-interface parallel ultra-high-definition image real-time processing and control device and method, and belongs to the technical field of image processing, and the device comprises a calculation processing module, a video input interface module, a video output interface module, an industrial automation control interface module and a data storage module. The calculation processing module is connected with the video input interface module, the user control and state indication module, the video output interface module, the industrial automation control interface module and the data storage module; the calculation processing module comprises an FPGA (Field Programmable Gate Array) processing unit and is used for receiving and transmitting data through various interfaces, executing temperature control, receiving multiple paths of video streams, carrying out parallel pipeline processing, outputting a processing result in real time and controlling various automatic mobile platforms; and the video input interface module comprises four HDMI (High Definition Multimedia Interface) 2.0 input interfaces and four Ethernet input interfaces. According to the invention, multiple inputs are compatible, parallel decoding and multi-core processor cooperative processing are realized, and the processing performance is improved.

The invention provides a multi-core processor cache coherence communication system based on FreeRTOS, and relates to the field of computer embedded systems, and the system comprises an application layer which comprises a plurality of tasks and is used for completing cross-core data interaction; the cache consistency communication layer is in communication connection with the application layer and the kernel layer; the cache consistency communication layer comprises a shared memory management module, a cache synchronization strategy scheduling module and a communication component synchronization adaptation module; the shared memory management module is used for tracking the cache state of the shared memory; the cache synchronization strategy scheduling module is used for selecting an optimal cache synchronization strategy according to the task and is linked with the task scheduler; the communication component synchronization adaptation module is used for identifying a corresponding shared memory block; the kernel layer comprises a memory manager, a task scheduler and a communication component; the communication component comprises queues, semaphores and event groups. According to the scheme, the problem of cache inconsistency is solved, and the correctness of cross-core data is ensured.

The invention discloses a satellite-borne soft platform virtual multi-core processor task synchronization method, which belongs to the technical field of ground test virtual simulation, and comprises the following steps: determining a time reference of system operation; and each core performs task cycle scheduling by using a system running time reference. According to the method, the synchronization of the task level of the virtual multi-core processor of the satellite-borne soft platform is realized by determining the running time reference of the system and controlling the starting and periodic execution of the multi-core task.

The invention discloses a dual-redundancy control method based on a high-performance multi-core processor and a related device, and belongs to the technical field of engine controllers, a dual-redundancy controller in a system comprises a master control unit and a slave control unit, the master control unit and the slave control unit respectively comprise a DSP and an FPGA, the DSP and the FPGA are connected through an EMIF bus, cores 0 are connected through an SRIO, and the cores 0 are connected through an SRIO bus. The cores 1 are connected through UART, and the core 0 is in communication connection with the cores 1; the FPGA of the master control unit and the FPGA of the slave control unit are respectively connected with corresponding cores 1, the core 1 of the master control unit is connected to the FPGA of the slave control unit through an STATE signal, and the core 1 of the slave control unit is connected to the FPGA of the master control unit through an STATE signal; the core 1 of the master control unit and the core 1 of the slave control unit are connected with the FPGA in two ways, one way is connected through a DOG signal, and the other way is connected through a WORK signal. According to the method, the conventional switching problem can be solved through hot standby redundancy switching, and the switching problem under the conditions of processor crash and recovery is solved.

The embodiment of the invention provides a storage medium access method and device, and the method comprises the steps that a first processor core determines N first access requests, the first access requests are access requests which are generated by the first processor core and are not executed, and the first access requests are used for requesting to access a storage area in a first access range of a storage medium; the first processor core determines a target access request from the N first access requests and executes the target access request, the target access request being a first access request independent of the second access request, the second access request is generated earlier than the depended first access request, and a second access range corresponding to the second access request is overlapped with a first access range corresponding to the depended first access request. The first processor core is any processor core in the multi-core processor, and the plurality of processor cores do not need to compete for an exclusive lock of a storage medium and can execute respective first access requests in parallel, so that the concurrency capability of the multi-core processor can be improved.

The invention discloses a target tracking method based on twin network lightweight deployment and a storage medium, and the method comprises the steps: cutting an image in an image data set into a template region image and a search region image; generating a template backbone network weight file, a search backbone network weight file and a cross-correlation tracking head network weight file through a twin convolutional neural network; performing quantitative perception training on the network model, and performing fine tuning on weight parameters of the three weight files to obtain a trained network model configured with a fine-tuned template backbone network weight file, a fine-tuned search backbone network weight file and a fine-tuned cross-correlation tracking head network weight file; and deploying the trained network model in a multi-core processor, finally inputting a target image into the trained network model, and reasoning and calculating a target position by the trained network model to realize target tracking. The balance between precision and speed in a target tracking algorithm is realized, and the speed of target tracking calculation is improved.

The invention provides an intelligent networked automobile environment perception sensor fault diagnosis box, and relates to the field of intelligent networked automobiles, the intelligent networked automobile environment perception sensor fault diagnosis box comprises a fault diagnosis box, a sensor detection chamber with an upward opening is arranged in the fault diagnosis box, and a host module is fixedly arranged on one side of the bottom in the sensor detection chamber; a fault sensor storage cabin is fixedly arranged at the bottom of the sensor detection chamber and located on the other side of the host module, and a turnover operation panel capable of being turned over is arranged on one side of the fault diagnosis box. Through the multi-core processor and the AI acceleration chip which are arranged in the host module, real-time analysis and processing of sensor data are realized, the fault diagnosis efficiency is remarkably improved, complex tasks such as point cloud density analysis, image quality detection and CAN communication verification are automatically completed through an AI algorithm, and compared with manual detection, the precision is higher, and the time consumption of single-time detection is shorter.

Providing processor core fault recovery without requiring system resets in multicore processor-based devices is disclosed herein. In some aspects, a processor-based device provides a plurality of processor cores that comprise a first processor core and a second processor core, with the first processor core configured to operate as a bootstrap processor core (BSP). The first processor core is configured to receive an interrupt corresponding to a registered timer event from a timer peripheral circuit, and, responsive to receiving the interrupt, transmit an interprocess interrupt (IPI) to the second processor core. The first processor core then determines whether a status update was successfully received from the second processor core in response to the IPI. If not, the first processor core performs one or more migration operations on the second processor core, masks the second processor core as offline for scheduling purposes, and blocks the second processor core from further health monitoring.

The application discloses a kind of dual-redundancy control method and related device based on high-performance multicore processor belongs to engine controller technical field, the system dual-redundancy controller includes main control unit and slave control unit, main control unit and slave control unit respectively include DSP and FPGA, between DSP and FPGA through EMIF bus connection, between core 0 through SRIO connection, between core 1 through UART connection, core 0 communication connection core 1;The FPGA of main control unit and slave control unit is connected corresponding core 1, the core 1 of main control unit is connected to the FPGA of slave control unit by STATE signal, and the core 1 of slave control unit is connected to the FPGA of main control unit by STATE signal;Between the core 1 and FPGA of main control unit and slave control unit, there are two connections, one is connected by DOG signal, and the other is connected by WORK signal.The application not only can solve the conventional switching problem by hot standby redundancy switching, but also solve the switching problem under the condition of processor crash and recovery.

The invention discloses a clock calibration method and device. The method comprises the following steps: respectively creating a first clock calibration task and a second clock calibration task; distributing the first clock calibration task to a target core in a multi-core processor of the base station equipment, and executing the first clock calibration task; and in response to a clock calibration request initiated by the cellular service of the base station equipment, switching the first clock calibration task to the second clock calibration task, and executing the second clock calibration task. According to the method and the device, the clock precision can be kept under the condition that the base station equipment does not run any cellular service, a processor core is not preempted to stabilize a communication system, and at least one periodic clock calibration task is run on the base station equipment, so that the clock precision of the base station equipment is improved, upper-layer service and clock calibration are decoupled, and the service performance of the base station equipment is improved. And the stability and reliability of the system are ensured.

Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.

The application provides a kind of high-reliability parallel running method of aerospace SPARC multi-core processor, and the multi-core processor chip includes at least two processor cores, and all processor cores of the multi-core processor chip are independently running and performing inter-core notification and synchronization;Multi-processor state register monitors the running state of processor core and activates multi-core running.The application independently deploys multiple software modules on multiple processor cores for parallel computing, breaking through the traditional aerospace single-core processor software design mode, so that the software can adapt to large-scale software, multi-module integration, high real-time and high reliability requirements.At the same time, the application expands the supporting technology related to aerospace multi-core processor, including multi-core loading, inter-core interrupt, peripheral management, data sharing area, inter-core dynamic monitoring, etc., which has great value for the development of comprehensive electronic, integrated control and health management aerospace software in the field of satellite payload software.

A method for data packet flow distribution in a multi-core processor by an electronic device is provided. The method includes receiving, by the electronic device, at least one data packet to be processed by the multi-core processor, determining, by the electronic device, whether a flow lock of a critical section of a data flow is acquired at a core, determining, by the electronic device, whether a threshold number of data packet from a flow queue is processed at the core upon successful flow lock acquisition, determining, by the electronic device, pending data packet to be processed in the flow queue upon processing the threshold number of data packet from the flow queue, creating, by the electronic device, a new trigger packet or event upon determining the pending data packet to be processed in the flow queue, releasing, by the electronic device, the flow lock of the critical section, and enqueuing the new trigger packet or event to a generic queue to be processed by other cores of the multi-core processor.

The application discloses a network communication method and device, electronic equipment and medium, and relates to the technical field of computers. The method is applied to a first core in a heterogeneous multi-core processor. The heterogeneous multi-core processor further comprises a network controller connected with the first core. The method comprises the following steps: in the case that the network controller receives first network data, the first network data is parsed to obtain a network port corresponding to the first network data; based on the network port, a target core corresponding to the first network data in the heterogeneous multi-core processor is determined; in the case that the target core is a second core, the first network data is stored in a preset shared memory corresponding to the second core, and a first interrupt signal is generated. Through the application, each core in the heterogeneous multi-core processor can communicate with the outside through one network controller.