Multicore processor, and system and method for debugging multicore processor

A technology of multi-core processors and processor cores, applied in the field of multi-core processors, can solve problems such as unfavorable multi-core processors and compatibility with debugging systems

Inactive Publication Date: 2011-06-22
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, both the test access port TAP and the JTAG emulator are specified in the IEEE1149.1 protocol. If they are

Method used

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  • Multicore processor, and system and method for debugging multicore processor
  • Multicore processor, and system and method for debugging multicore processor
  • Multicore processor, and system and method for debugging multicore processor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] The purpose of this embodiment is to provide a multi-core processor, the test access port TAP of each processor core is a standard form, and the port of the JTAG emulator for debugging is a standard JTAG port.

[0039] refer to Figure 4 , a multi-core processor, the communication between the test access port TAP of each processor core and the JTAG emulator is realized by a chip-level TAP support module. The chip-level TAP support module is located inside the chip, and is connected to the test access port TAP of each processor core, and the test access port TAP of each processor core is connected to the chip-level TAP support module in parallel. The chip-level TAP support module is provided with an external interface, and the external interface includes a TDI interface for receiving test data, a TDO interface for feeding back test data output to the emulator, a TCK interface for receiving a test clock signal, and a TCK interface for receiving test data. TMS interface f...

Embodiment 2

[0048] The multi-core processor in Embodiment 1 may have the following problems when debugging: if the processor core to be tested enters the debugging state, and other processor cores do not enter the debugging state, it is possible to make the debugging result reduced reliability. Because, when debugging a certain processor core, operations such as I / O (input and output), reading and writing memory of other processor cores may cause the variable value of the processor core in the debugging state to change, so that The reliability of the commissioning results has been questioned. At the same time, there is another situation, that is, when the system clock supply of a certain processor core is insufficient or the system power supply is insufficient, if it is forced to debug, the reliability of the debugging results will be questioned because of the above-mentioned situation , the processor core cannot be debugged in real time.

[0049]Therefore, on the basis of Embodiment 1,...

Embodiment 3

[0057] Please refer to Figure 4 A debugging system for a multi-core processor includes a debugging host, an emulator and a multi-core processor. The debugging host is connected with the emulator, and is used to transmit information such as debugging data and debugging instructions to the multi-core processor through the emulator, and then debug the multi-core processor. The emulator is a standard JTAG emulator, which is connected with the multi-core processor by a standard TDI, TDO, TMS, TCK and / or TRST interface, and the multi-core processor has the method described in embodiment 1 and / or embodiment 2. structure and function.

[0058] Please refer to Figure 9 , a debugging method for a multi-core processor, comprising steps:

[0059] Step A, the debugging host cyclically visits the test access port controller until the debug response signal sent by the test access port controller is obtained;

[0060] Step B, the debugging host configures the test access terminal contro...

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Abstract

The invention discloses a multicore processor. The multicore processor comprises a test access port controller and a debugging connector; the test access port controller is provided with an interface connected with a joint test action group (JTAG) simulator; the debugging connector is connected with test access ports of all the cores of the processor; all the test access ports are connected with the debugging connector in parallel; and the test access port controller is used for controlling the debugging connector to connect the cores of the processor to be tested to the simulator. In the processor with the structure, the designs of the standard JTAG port and the test access ports are not needed to be changed. The invention also discloses a system and a method for debugging the multicore processor.

Description

technical field [0001] The invention relates to a multi-core processor, a debugging system and a debugging method for the multi-core processor. Background technique [0002] A multi-core processor refers to the simultaneous integration of two or more computing cores in one processor chip. Compared with single-core processors, multi-core processors have faster computing speed and more efficient power utilization. However, compared to single-core processors, the debugging of multi-core processors is indeed complicated. [0003] In the prior art, single-core processors such as CPU and DSP usually use a JTAG (Joint Test Action Group, Joint Test Action Group) interface to access their internal circuit logic for debugging. JTAG is an international standardized protocol compatible with IEEE1149.1 for internal testing of chips. The standard JTAG interface generally has mode selection TMS, clock TCK, data input TDI and data output TDO, and may also include an optional TRST for tes...

Claims

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Application Information

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IPC IPC(8): G06F11/22
Inventor 薛晓旭王新安胡子一
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL
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