Method and system for uncorrectable error detection

Abstract

A system, method and program product for utilizing error correction code (ECC) logic to detect multi-bit errors. In one embodiment, a first test pattern and a second test pattern are applied to a set of hardware bit positions. The first and second patterns are multiple logic level patterns and the second test pattern is the logical complement of the first test pattern. The first and second test patterns are utilized by the ECC logic to detect correctable errors having n or fewer bits. One or more bit positions of a first correctable error occurring responsive to applying the first test pattern are determined and one or more bit positions of a second correctable error occurring responsive to applying the second test pattern are determined. The determined bit positions of the first and second correctable errors are processed to identify a multiple-bit error within the set of hardware bit positions.

Description

BACKGROUND OF THE INVENTION[0001]1. Technical Field[0002]The present invention relates generally to error correction codes, and in particular, to utilizing correctable error analysis to identify otherwise undetected multi-bit errors.[0003]2. Description of the Related Art[0004]Many hardware diagnostic tests for memory arrays or buses rely on hardware-generated error correction codes (ECCs) which detect and correct single-bit errors known as correctable errors (CEs). Such ECCs are often further enabled to detect, but not correct, multi-bit errors known as uncorrectable errors (UEs). A primary goal of ECC diagnostics testing is to identify the locations of UEs so that hardware containing UEs can be deconfigured.[0005]Robust ECC testing procedures have long been recognized as a practical necessity for main storage on large scale computer systems such as the S / 390 Parallel Enterprise Server systems available from IBM Corporation. S / 390 and IBM are registered trademarks, and S / 390 Parall...

AI Technical Summary

Benefits of technology

[0010]A system, method and program product for utilizing error correction code (ECC) logic to detect multi-bit errors are disclosed herein. In one embodiment, a first test pattern and a second test pattern are applied to a set of hardware bit positions. The first and second patterns are multiple logic level patterns and the second test pattern is the logical complement of the first test pattern. The first and second test patterns are utilized by the ECC logic to detect correctable errors having n or fewer bits. One or more bit positions of a first correctable error occurring responsive to applying the first test pattern are determined and one or more bit positions of a second correctable error occurring responsive to applying the second test pattern are determined. The determined bit positions of the first and second correctable errors are processed to identify a multiple-bit error within the set of hardware bit positions.

Problems solved by technology

Such ECCs are often further enabled to detect, but not correct, multi-bit errors known as uncorrectable errors (UEs).

UE detection becomes even more difficult when the faulty bit locations are not persistently stuck at particular levels, but instead fail intermittently.

While improving the reliability of detecting UEs having bad bits stuck at multiple logic levels, several problems remain unresolved.

Conventional multi-pattern ECC testing also fails to adequately address the problem of intermittently occurring multiple-bit errors.

For both the bit spread issue and intermittent fault issue, increasing the number of patterns expands UE detection coverage, but also increases the costs associated with extra test pattern coverage.

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