Method of manufacturing semiconductor element metal gate stack

A metal gate and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of component performance change, p-type metal gate resistance increase, etc., to reduce mismatch and RC Delayed, negativity-increased effects

Inactive Publication Date: 2011-08-10
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, the n-type metal layer will be deposited unevenly in the recessed p-type metal gate, resulting in an increase in t

Method used

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  • Method of manufacturing semiconductor element metal gate stack
  • Method of manufacturing semiconductor element metal gate stack
  • Method of manufacturing semiconductor element metal gate stack

Examples

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Embodiment Construction

[0039] figure 1 A flowchart of an embodiment of a method 100 for fabricating a semiconductor device having a metal gate stack is disclosed in accordance with various aspects of the present invention. Figure 2 to Figure 7 In view of one or more embodiments of the present invention, schematic cross-sectional views of a semiconductor structure 200 at different process stages are disclosed. For a description of the semiconductor structure 200 and its manufacturing method 100, please refer to Figure 1 to Figure 7 .

[0040] see figure 1 , figure 2 The method 100 for manufacturing a semiconductor device of the present invention begins at step 102 , providing a semiconductor substrate 210 . The semiconductor substrate 210 includes silicon, and may optionally include germanium, silicon germanium or other suitable semiconductor materials. The semiconductor substrate 210 also includes various isolation structures 220 such as shallow trench isolations formed in the substrate to s...

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Abstract

The invention provides a method of manufacturing a semiconductor element metal gate stack. The present disclosure provides a method that includes forming a high k dielectric layer on a semiconductor substrate; forming a polysilicon layer on the high k dielectric layer; patterning the high k dielectric layer and polysilicon layer to form first and second dummy gates in first and second field effect transistor (FET) regions, respectively; forming an inter-level dielectric (ILD); applying a first CMP process to the semiconductor substrate, exposing the first and second dummy gates; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a first metal electrode in the first gate trench; applying a second CMP process; forming a mask covering the first FET region and exposing the second dummy gate; thereafter removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a second metal electrode in the second gate trench; and applying a third CMP process. The invention maintains the integration of metal gate electrode and the expected working function and improves the circuit effect.

Description

technical field [0001] The present invention relates to a manufacturing method of a semiconductor element, in particular to a manufacturing method of a semiconductor element forming metal gate stacks. Background technique [0002] When a semiconductor device such as a metal oxide semiconductor field effect transistor (MOSFET) is scaled by different technologies, high-k dielectric materials and metals are suitable for forming a gate stack. However, in the method of forming metal gate stacks of n-type metal-oxide-semiconductor (nMOS) transistors and p-type metal-oxide-semiconductor (pMOS) transistors, different problems arise when integrating processes and materials. For example, when the p-type metal gate of a p-type metal-oxide-semiconductor (pMOS) transistor is exposed to a process that removes polysilicon to form an n-type metal gate, the aluminum filling the p-type metal gate electrode can be damaged and recessed . For example, the n-type metal layer is deposited uneven...

Claims

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Application Information

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IPC IPC(8): H01L21/28H01L21/8238H01L21/822
CPCH01L27/0629H01L21/823842H01L29/78H01L29/4966H01L29/66545
Inventor 张立伟庄学理
Owner TAIWAN SEMICON MFG CO LTD
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