22 results about "Metal gate electrodes" patented technology

Disclosed is a semiconductor device including a metal gate electrode optimized for a peripheral region. The semiconductor device includes a substrate including a first NMOS region and a second NMOS region whose line width is different from a line width of the first NMOS region; a first conductive pattern including a stacked structure of a first gate dielectric layer and a first metal electrode over the substrate of the first NMOS region, and including a first high-k layer interposed at an interface between the first gate dielectric layer and the first metal electrode and containing a dipole-inducing chemical species; and a second conductive pattern including a stacked structure of a second gate dielectric layer and a second metal electrode over the substrate of the second NMOS region, and including a second high-k layer interposed at an interface between the second gate dielectric layer and the second metal electrode.

The invention relates to the technical field of semiconductor optoelectronic devices, in particular to a gallium oxide-based fin type solar-blind ultraviolet photoelectric transistor and a preparation method thereof. Comprising a substrate; the Ga2O3 thin film is arranged on the substrate; the periodic fin-type channel structure is located in the region of the Ga2O3 film and is formed by an etching process, the width of a single fin is the same as the interval between adjacent fins, and the height of the fins is equal to the thickness of the Ga2O3 film; the source electrode and the drain electrode are located at the two ends of the fin array of the periodic fin type channel structure respectively and form ohmic contact with the Ga2O3 thin film; the gate dielectric layer covers the surface of the periodic fin type channel structure; and the metal gate electrode covers the surface of the gate dielectric layer to form a surrounding type gate control structure. The method has the advantages that the short channel effect is effectively inhibited through the three-dimensional grid-control structure of the fin-type transistor, and extremely low dark current is kept while the submicron channel length is realized; localization and absorption of solar-blind ultraviolet light in a channel are remarkably enhanced, and quantum efficiency and photoelectric gain are improved.

The invention provides a high electron mobility transistor and a preparation method thereof, and belongs to the technical field of semiconductors. The high electron mobility transistor comprises an epitaxial layer, a gate electrode and connecting metal, the gate electrode is located at one side of the epitaxial layer, the gate electrode comprises a gate bus and a plurality of gate structures, the gate bus surrounds the plurality of gate structures, and the plurality of gate structures are respectively connected with the gate bus; the connecting metal is located on the side, back to the epitaxial layer, of the gate electrode and comprises a connecting bus and a gate connecting structure, the surrounding track of the connecting bus is consistent with the surrounding track of the gate bus, the connecting bus is connected with the gate bus, and the gate connecting structure is located in the surrounding area of the connecting bus and connected with the connecting bus. According to the invention, physical shielding and electric shielding effects can be realized at the same time.

A transistor device and a method for fabricating the gate of the transistor device are disclosed. In an embodiment, the transistor device includes a semiconductor substrate having a main surface, a cell field including a plurality of transistor cells, and an edge termination region surrounding the cell field in the lateral direction. The cell field includes a gate trench in the main surface of the semiconductor substrate, a gate dielectric padding the gate trench, a metal gate electrode disposed in the gate trench on the gate dielectric, and an electrically insulating cap disposed on the metal gate electrode and within the gate trench.

The application discloses a flexible injectable organic electrochemical transistor sensor for protein immunological marker detection and a preparation method and application thereof, and relates to the technical field of biochemical sensors, and comprises a bottom flexible substrate, a metal source electrode, a metal drain electrode and a metal gate electrode arranged on the surface of the flexible substrate, and a top encapsulation layer, wherein an organic semiconductor conductive channel is arranged between the metal source electrode and the metal drain electrode, the metal gate electrode is arranged in a coplanar mode with the organic semiconductor conductive channel, the top encapsulation layer plays an encapsulation role, and the organic semiconductor conductive channel and the metal gate electrode are exposed after encapsulation; the metal gate electrode is modified with a monolayer of 11-mercapto undecanoic acid self-assembly, and an amino-modified single-stranded DNA molecule aptamer is covalently coupled on the monolayer. The sensor can be used for detection of various protein molecules including IFN-gamma tumor markers.

A transition metal dichalcogenide (TMD) transistor includes a substrate, an n-type two-dimensional (2D) TMD layer, a metal source electrode, a metal drain electrode, and a gate dielectric. The substrate has a top portion that is an insulating layer, and the n-type 2D TMD layer is on the insulating layer. The metal source electrode, the metal drain electrode, and the gate dielectric are on the n-type 2D TMD layer. The metal gate electrode is on top of the gate dielectric and is between the metal source electrode and the metal drain electrode.

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and relates to the technical field of semiconductors, the semiconductor device comprises a logic unit located on a substrate, and the logic unit comprises a first transistor and a second transistor which are distributed along a row direction parallel to the substrate; the first transistor comprises a first semiconductor layer and a first metal gate electrode; a first oxide insulating layer is arranged between the first semiconductor layer and the first metal gate electrode; the second transistor comprises a second semiconductor layer and a second metal gate electrode; a second oxide insulating layer is arranged between the second semiconductor layer and the second metal gate electrode; the first transistor is an N-type transistor, the second transistor is a P-type transistor, and both the first transistor and the second transistor are junctionless transistors; the first semiconductor layer and the second semiconductor layer extend in the direction perpendicular to the substrate. According to the semiconductor device provided by the embodiment of the invention, relatively high integration density can be realized, and the manufacturing process is simple.

This invention relates to a silicon MOS quantum bit device and its fabrication method. The silicon MOS quantum bit device employs a dual-layer gate architecture combining a polysilicon global gate and a metal local gate: the first layer is a polysilicon global gate, covering most of the active region of the quantum dot, enabling potential shielding and static coarse tuning; the second layer is a localized metal fine gate, with each metal gate electrode corresponding to a single quantum dot, enabling near-field fine tuning and high-speed gating. The combination of the polysilicon global gate and the metal local gate can reduce charge noise and improve coherence time while achieving precise and high-speed control of the quantum dot. The disclosed method is based on mature CMOS process technology, suitable for reproducible manufacturing on large-size wafers, and can significantly improve the proportion of usable quantum bits and device yield.

The invention belongs to the technical field of semiconductors, and particularly discloses a depletion type gallium nitride chip, a preparation method thereof and a cascade packaging device.The depletion type gallium nitride chip comprises a gate electrode, a first dielectric layer, a second dielectric layer, a third dielectric layer and a first field plate unit at least comprising two layers of field plates, the first field plate unit is at least partially located between the second dielectric layer and the third dielectric layer, and the gate electrode is located at the end, close to the source electrode, of the first field plate unit and located between the third dielectric layer and the laminated structure. The first dielectric layer, the second dielectric layer, the gate electrode and the first field plate unit are all located between the source electrode ohmic metal and the drain electrode ohmic metal; and the source electrode ohmic metal, the gate electrode and the first field plate unit are arranged on the same layer. According to the depletion type gallium nitride chip, the technology is simplified, meanwhile, multiple layers of field plates can be formed on one dielectric layer, the flatness of the chip is better, and a packaged device can be better applied to a circuit.

A semiconductor device includes a gate structure disposed over a channel region, and a source / drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

A semiconductor structure is provided that includes a tunable and shared non-conductive layer as part of a gate stack of at least a pair of nanosheet GAA transistors with a shared metal gate electrode. The semiconductor structure has a tunable non-conductive material / gate dielectric area ratio where the non-conductive material is not constrained to a periphery of the nanosheet stack cross section.

The invention relates to an electroless plating method for metal gate filler. In a gate replacement process for a nanosheet FinFET device, embodiments employ an electrochemical process to deposit a metal gate electrode in a gate opening. Bottom-up deposition of the filler material for the metal gate electrode may be achieved using an accelerator and an inhibitor.

Device comprising: a substrate (110); an interface layer (210) formed above the substrate (110), wherein the interface layer (210) has a dipole-penetrated section (210A); a gate dielectric layer (430) formed above the interface layer (210); and a metal gate electrode formed above the gate dielectric layer (430), wherein the dipole-penetrated section (210A) comprises yttrium oxide Y2O3, niobium oxide Nb2O5, titanium oxide TiO5, boron oxide B2O3, phosphorus pentoxide P2O5 or phosphorus trioxide P2O3.

The application discloses a MESFET device based on flexoelectric effect and photoelectric effect enhancement, which comprises a laser light source, a silicon substrate, an insulating layer, a metal gate electrode, a two-dimensional semiconductor layer, a first source-drain electrode and a second source-drain electrode. The insulating layer is arranged on the silicon substrate; the metal gate electrode and the two-dimensional semiconductor layer are arranged on the insulating layer, and the two-dimensional semiconductor layer covers the metal gate electrode. The first source-drain electrode and the second source-drain electrode are arranged on the two-dimensional semiconductor layer and are located on opposite sides of the metal gate electrode respectively. The laser light source is directed towards the two-dimensional semiconductor layer. The first source-drain electrode and the second source-drain electrode each comprise an electrode main body. A plurality of pressing needle tips are arranged on the electrode main body of the first source-drain electrode and / or the second source-drain electrode. The tips of the pressing needle tips are directed towards the two-dimensional semiconductor layer. Under the action of the flexoelectric field, the source-drain current of the MESFET device is more easily saturated, and the driving capacity of the source-drain current of the MESFET device is increased.

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and relates to the technical field of semiconductors, and the semiconductor device comprises a plurality of control units which are distributed in different layers, are stacked in a direction perpendicular to a substrate, and are periodically distributed; each control unit comprises a first transistor and a second transistor which are located on the same layer and distributed in the row direction parallel to the substrate. The first transistor is a P-type transistor and comprises a first semiconductor layer, a first metal gate electrode and a first oxide insulating layer located between the first semiconductor layer and the first metal gate electrode; the first semiconductor layer extends along the row direction; the second transistor is an N-type transistor and comprises a second semiconductor layer, a second metal gate electrode and a second oxide insulating layer located between the second semiconductor layer and the second metal gate electrode; the second semiconductor layer extends in a row direction. According to the semiconductor device provided by the embodiment of the invention, relatively high integration density can be realized, and the manufacturing process is simple.

This invention belongs to the field of semiconductor technology and discloses a depletion-type gallium nitride (GaN) chip and its fabrication method. The fabrication method includes the following steps: after growing a stacked structure on a substrate, a first dielectric layer is first grown on its top surface and a first step is formed by wet etching; then a second dielectric layer is grown on the first step and a second step and a single-sided gate trench are formed by wet etching; a third step is formed by dry etching, with the single-sided gate trench located near the end of the second step and away from the third step; source electrode ohmic holes and drain electrode ohmic holes are formed by etching downwards from the top surface of the stacked structure, and the wafer is subjected to a first annealing; bottom metal and top metal are grown, and source electrode ohmic metal, drain electrode ohmic metal, gate electrode and first field plate unit are formed by dry etching; the wafer is then subjected to a second annealing; finally, a third dielectric layer is grown, and source electrode and drain electrode are formed. The fabrication method of the depletion-type GaN chip of this invention simplifies the process and results in a chip with better flatness.

The embodiment of the utility model provides a TOPCon battery structure, and the battery structure comprises an N-type substrate which is provided with a first surface and a second surface which are opposite to each other, and a p + doping layer, a passivation layer, a first antireflection layer and a first magnesium fluoride layer which are located on the first surface of the N-type substrate and are sequentially stacked, the tunneling oxide layer, the n + doping layer, the second antireflection layer and the second magnesium fluoride layer are sequentially stacked on the second surface of the N-type substrate, the first metal gate electrode penetrates through the first magnesium fluoride layer, the first antireflection layer and the passivation layer and is in contact with the p + doping layer, and the second metal gate electrode penetrates through the second magnesium fluoride layer and the second antireflection layer and is in contact with the n + doping layer.

A sacrificial layer is formed over a first channel structure of an N-type transistor (NFET) and over a second channel structure of a P-type transistor (PFET). A PFET patterning process is performed at least in part by etching away the sacrificial layer in the PFET while protecting the NFET from being etched. After the PFET patterning process has been performed, a P-type work function (WF) metal layer is deposited in both the NFET and the PFET. An NFET patterning process is performed at least in part by etching away the P-type WF metal layer and the sacrificial layer in the NFET while protecting the PFET from being etched. After the NFET patterning process has been performed, an N-type WF metal layer is deposited in both the NFET and the PFET.

This application relates to electroless plating methods for metal gate fill. In a gate replacement process for nanosheet FinFET devices, embodiments employ an electrochemical process to deposit a metal gate electrode in a gate opening. Promoters and inhibitors can be used to achieve bottom-up deposition for the fill material of the metal gate electrode.

A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.

The application discloses a preparation method of a metal gate and a preparation method of a CMOS device. The P-type metal work function layer located outside a PMOS region pseudo gate trench and at least a notch in the PMOS region pseudo gate trench is removed, so that the width of the PMOS region pseudo gate trench at least the notch is increased, and the top height of the PMOS region pseudo gate trench is also reduced, thereby greatly reducing the aspect ratio of the PMOS region pseudo gate trench, mainly reducing the aspect ratio of the notch of the PMOS region pseudo gate trench, and then when filling metal into the PMOS region pseudo gate trench as a metal gate electrode layer, it is not easy to cause a void due to overhanging at the top of the PMOS region pseudo gate trench, that is, the filling effect of filling metal into the PMOS region pseudo gate trench is improved, which greatly increases the reliability of the CMOS device and improves the yield of the CMOS device.

A transistor device includes a semiconductor substrate and a gate structure formed at the upper surface of the substrate. The gate structure includes a metal gate electrode and a gate insulating layer overlying the metal gate electrode, where edges of the gate insulating layer correspond to edges of the metal gate electrode. The transistor device also includes a first dielectric layer formed over the gate structure, and a first interconnect metal layer formed over the first dielectric layer. A portion of the first interconnect metal layer forms a field plate proximate to the gate structure, and a portion of the gate insulating layer and a portion of the first dielectric layer are present between the gate electrode and the field plate.