77 results about "Metal gate electrodes" patented technology

A semiconductor structure including a stacked forksheet FET is provided. The semiconductor structure includes a frontside gate cut structure that physically isolates a bottom forksheet FET from a top forksheet FET. The frontside gate cut structure provides a physical barrier that allows for a first metal gate electrode to be removed from the top forksheet FET without negatively impacting (i.e., removing) the first metal gate electrode of the bottom FET. After removal of the first metal gate electrode from the top forksheet FET, a second metal gate electrode can be formed in the area of the top forksheet FET which was previously occupied by the first metal gate electrode.

The invention provides a preparation method of a metal SIN layer-semiconductor structure low-loss source-drain GaN power device, and belongs to the technical field of electronic elements, and the method comprises the steps: growing a high-purity GaN layer on a gallium nitride substrate through molecular beam epitaxy to control the point location density; depositing an SIN dielectric layer through radio frequency magnetron sputtering; depositing a metal gate electrode by electron beam evaporation and ensuring accurate alignment; defining source and drain regions through photoetching and plasma etching; forming a high-concentration doped region by adopting ion implantation; performing thermal annealing treatment according to the calculation result of the thermodynamic parameter equation set; determining the optimal annealing parameter of the ohmic contact by using a traveling salesman problem optimization algorithm; depositing a Ti / Al / Ni / Au multilayer metal source drain electrode; and carrying out a device packaging test, and analyzing and optimizing process parameters based on the loss matrix. According to the method, through accurate process control and multi-physical field coupling optimization, the problem of high loss of the source and drain regions of the GaN power device is effectively solved.

Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

Disclosed is a semiconductor device including a metal gate electrode optimized for a peripheral region. The semiconductor device includes a substrate including a first NMOS region and a second NMOS region whose line width is different from a line width of the first NMOS region; a first conductive pattern including a stacked structure of a first gate dielectric layer and a first metal electrode over the substrate of the first NMOS region, and including a first high-k layer interposed at an interface between the first gate dielectric layer and the first metal electrode and containing a dipole-inducing chemical species; and a second conductive pattern including a stacked structure of a second gate dielectric layer and a second metal electrode over the substrate of the second NMOS region, and including a second high-k layer interposed at an interface between the second gate dielectric layer and the second metal electrode.

A memory device includes a first high-k gate dielectric layer disposed in a semiconductor substrate. A top surface of the first high- k gate dielectric layer is higher than a top surface of the semiconductor substrate. The memory device also includes a first metal gate electrode layer disposed over the first high-k gate dielectric layer. A lower portion of the first metal gate electrode layer is surrounded by the first high-k gate dielectric layer, and a width of an upper portion of the first metal gate electrode layer is greater than a width of the lower portion of the first metal gate electrode layer. The memory device further includes a first dielectric portion disposed over the first metal gate electrode layer.

The invention provides a gate injection type ferroelectric field effect transistor and a preparation method thereof, and belongs to the technical field of micro-nano electronics. The ferroelectric field effect transistor structurally comprises a semiconductor substrate, a highly-doped source region, a highly-doped drain region, a metal gate electrode and a gate stack, the structure of the gate stack sequentially comprises a channel insulating layer, a ferroelectric layer, a charge trapping layer and a gate insulating layer from bottom to top, the charge trapping layer comprises three layers of materials, and the structure of the charge trapping layer sequentially comprises a layer of charge trapping material, a layer of barrier layer insertion layer and a layer of charge trapping material from bottom to top; the metal gate electrode is located on the gate stack, and the highly-doped source region and the highly-doped drain region are located on the two sides of a channel region below the gate stack respectively. By introducing the charge trapping layer and inserting the barrier layer in the charge trapping layer, the storage characteristic of the device is improved, the preparation method is simple, and a material system is compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process; the storage window and the retention characteristic of the gate injection type ferroelectric field effect transistor are improved, and the gate injection type ferroelectric field effect transistor has high practical value.

A semiconductor structure includes gate spacers disposed over a semiconductor layer, a hafnium-containing dielectric layer, where a first portion of the hafnium-containing dielectric layer having a first thickness is disposed over the semiconductor layer and a second portion of the hafnium-containing dielectric layer having a second thickness is disposed along sidewalls of the gate spacers, and where the first thickness is greater than the second thickness, and a metal gate electrode disposed over the hafnium-containing dielectric layer and between the gate spacers.

The invention provides a forming method of a semiconductor device and the semiconductor device. The method comprises the following steps: depositing a gate oxide layer with a high dielectric constant on a preset substrate; forming a decomposable film side wall layer on the side wall of the groove; depositing a metal gate electrode material to form a metal gate electrode in the groove, and removing the gate oxide layer above the interlayer dielectric layer; depositing a porous thin film layer, etching the gate oxide layers on the side walls of the two sides of the groove and the interlayer dielectric layer in contact with the gate oxide layers, and filling metal to form a contact hole electrode in contact with the source-drain active region; and performing an annealing process to decompose the decomposable film side wall layer and volatilize the decomposable film side wall layer through the porous film layer, so that an air layer is formed on the decomposable film side wall layer between the contact hole and the metal gate electrode. According to the invention, the gate oxide layer with a high dielectric constant between the contact hole and the metal gate electrode is replaced by the air layer with a low dielectric constant, so that the stray capacitance between the metal gate electrode and the source-drain contact hole electrode is reduced, and the RC delay is reduced.

The invention relates to the technical field of semiconductor optoelectronic devices, in particular to a gallium oxide-based fin type solar-blind ultraviolet photoelectric transistor and a preparation method thereof. Comprising a substrate; the Ga2O3 thin film is arranged on the substrate; the periodic fin-type channel structure is located in the region of the Ga2O3 film and is formed by an etching process, the width of a single fin is the same as the interval between adjacent fins, and the height of the fins is equal to the thickness of the Ga2O3 film; the source electrode and the drain electrode are located at the two ends of the fin array of the periodic fin type channel structure respectively and form ohmic contact with the Ga2O3 thin film; the gate dielectric layer covers the surface of the periodic fin type channel structure; and the metal gate electrode covers the surface of the gate dielectric layer to form a surrounding type gate control structure. The method has the advantages that the short channel effect is effectively inhibited through the three-dimensional grid-control structure of the fin-type transistor, and extremely low dark current is kept while the submicron channel length is realized; localization and absorption of solar-blind ultraviolet light in a channel are remarkably enhanced, and quantum efficiency and photoelectric gain are improved.

A semiconductor structure includes an interfacial layer disposed over a semiconductor channel region, a metal oxide layer disposed over the interfacial layer, a high-k gate dielectric layer disposed over the metal oxide layer, a metal halide layer disposed over the high-k gate dielectric layer, and a metal gate electrode disposed over the high-k gate dielectric layer. The metal oxide layer and the interfacial layer form a dipole moment. The metal oxide layer includes a first metal. The metal halide layer includes a second metal different from the first metal.

The invention provides a high electron mobility transistor and a preparation method thereof, and belongs to the technical field of semiconductors. The high electron mobility transistor comprises an epitaxial layer, a gate electrode and connecting metal, the gate electrode is located at one side of the epitaxial layer, the gate electrode comprises a gate bus and a plurality of gate structures, the gate bus surrounds the plurality of gate structures, and the plurality of gate structures are respectively connected with the gate bus; the connecting metal is located on the side, back to the epitaxial layer, of the gate electrode and comprises a connecting bus and a gate connecting structure, the surrounding track of the connecting bus is consistent with the surrounding track of the gate bus, the connecting bus is connected with the gate bus, and the gate connecting structure is located in the surrounding area of the connecting bus and connected with the connecting bus. According to the invention, physical shielding and electric shielding effects can be realized at the same time.

A device includes a gate stack and a channel layer over the gate stack. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The semiconducting oxide layer has a thickness between approximately 1 μm and approximately 30 μm.

A transistor device and a method for fabricating the gate of the transistor device are disclosed. In an embodiment, the transistor device includes a semiconductor substrate having a main surface, a cell field including a plurality of transistor cells, and an edge termination region surrounding the cell field in the lateral direction. The cell field includes a gate trench in the main surface of the semiconductor substrate, a gate dielectric padding the gate trench, a metal gate electrode disposed in the gate trench on the gate dielectric, and an electrically insulating cap disposed on the metal gate electrode and within the gate trench.

The application discloses a flexible injectable organic electrochemical transistor sensor for protein immunological marker detection and a preparation method and application thereof, and relates to the technical field of biochemical sensors, and comprises a bottom flexible substrate, a metal source electrode, a metal drain electrode and a metal gate electrode arranged on the surface of the flexible substrate, and a top encapsulation layer, wherein an organic semiconductor conductive channel is arranged between the metal source electrode and the metal drain electrode, the metal gate electrode is arranged in a coplanar mode with the organic semiconductor conductive channel, the top encapsulation layer plays an encapsulation role, and the organic semiconductor conductive channel and the metal gate electrode are exposed after encapsulation; the metal gate electrode is modified with a monolayer of 11-mercapto undecanoic acid self-assembly, and an amino-modified single-stranded DNA molecule aptamer is covalently coupled on the monolayer. The sensor can be used for detection of various protein molecules including IFN-gamma tumor markers.

A semiconductor device includes a gate structure disposed over a channel region and a source / drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.

The present application discloses a memory device and a method for fabricating the same. The memory device includes a semiconductor substrate having an active area, and a word line structure extending across the active area. The word line structure includes a metal gate electrode layer and a high-k gate dielectric layer surrounding the metal gate electrode layer. The memory device also includes a first source / drain region and a second source / drain region disposed in the active area and at opposite sides of the word line structure. The memory device further includes a bit line structure disposed over and electrically connected to the first source / drain region, and a capacitor disposed over and electrically connected to the second source / drain region.

A memory device includes a semiconductor substrate having an active area, and a word line structure extending across the active area. The word line structure includes a metal gate electrode layer and a high-k gate dielectric layer surrounding the metal gate electrode layer. The memory device also includes a first source / drain region and a second source / drain region disposed in the active area and at opposite sides of the word line structure. The memory device further includes a bit line structure disposed over and electrically connected to the first source / drain region, and a capacitor disposed over and electrically connected to the second source / drain region.

The application discloses a high-heat-dissipation sapphire-based heterojunction half-bridge device, which comprises a substrate, a low-measuring area which is composed of a first buffer layer, a first channel layer, a first heterojunction channel, a first barrier layer, a first metal source electrode, a first metal drain electrode and a first metal gate electrode, a high-measuring area which is composed of a second buffer layer, a second channel layer, a second heterojunction channel, a second barrier layer, a second metal source electrode, a second metal drain electrode and a second metal gate electrode, and a groove area which is composed of an insulating medium layer and a heat-conducting medium layer. The device can dissipate heat in the device body through the groove area, and the heat dissipation performance of the device can be improved.

A memory device includes a semiconductor substrate having an active area, and a word line structure extending across the active area. The word line structure includes a metal gate electrode layer and a high-k gate dielectric layer surrounding the metal gate electrode layer. The memory device also includes a first source / drain region and a second source / drain region disposed in the active area and at opposite sides of the word line structure. The memory device further includes a bit line structure disposed over and electrically connected to the first source / drain region, and a capacitor disposed over and electrically connected to the second source / drain region.

Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

A memory device includes a first high-k gate dielectric layer disposed in a semiconductor substrate. A top surface of the first high-k gate dielectric layer is higher than a top surface of the semiconductor substrate. The memory device also includes a first metal gate electrode layer disposed over the first high-k gate dielectric layer. A lower portion of the first metal gate electrode layer is surrounded by the first high-k gate dielectric layer, and a width of an upper portion of the first metal gate electrode layer is greater than a width of the lower portion of the first metal gate electrode layer. The memory device further includes a first dielectric portion disposed over the first metal gate electrode layer.

A semiconductor structure includes a substrate, a nanowire disposed over the substrate, a metal gate electrode layer and a gate dielectric layer. A dielectric layer is formed on the substrate. The nanowire has a first portion and a second portion. The nanowire has a first portion and a second portion, the first portion of the nanowire comprises a first semiconductor layer and a second semiconductor layer surrounded by the first semiconductor layer, the second portion comprises the second semiconductor layer. The metal gate electrode layer surrounds the first portion of the nanowire. The gate dielectric layer is disposed between the metal gate electrode layer and the nanowire.

This invention provides a method for forming a semiconductor device and the semiconductor device itself. The method includes: depositing a gate oxide layer with a high dielectric constant onto a predetermined substrate; forming a degradable thin film sidewall layer on the sidewalls of a trench; depositing a metal gate electrode material to form a metal gate electrode within the trench; removing the gate oxide layer above the interlayer dielectric layer; depositing a porous thin film layer; etching the gate oxide layer on both sides of the trench and the interlayer dielectric layer in contact with the gate oxide layer; and filling with metal to form contact hole electrodes in contact with the source / drain active regions; and performing an annealing process to decompose the degradable thin film sidewall layer and allow it to volatilize through the porous thin film layer, thereby forming an air layer between the contact hole and the metal gate electrode. This invention replaces the high dielectric constant gate oxide layer between the contact hole and the metal gate electrode with a low dielectric constant air layer, reducing the parasitic capacitance between the metal gate electrode and the source / drain contact hole electrodes, thereby reducing RC delay.

The semiconductor device includes: a gate structure disposed over a channel region and a source / drain region. The gate structure includes: a gate dielectric layer located over the channel region; one or more work function adjustment material layers located over the gate dielectric layer; and a metal gate electrode layer located over the one or more work function adjustment material layers. The one or more work function adjustment layers include an aluminum-containing layer, and a diffusion barrier layer is disposed at least at one of a bottom and a top of the aluminum-containing layer. The diffusion barrier layer is one or more of a titanium-rich layer, a titanium-doped layer, a tantalum-rich layer, a tantalum-doped layer, and a silicon-doped layer. Embodiments of the present application also relate to a method of manufacturing a semiconductor device.

The present disclosure provides a memory device including a first high-k gate dielectric layer disposed in a semiconductor substrate. An upper surface of the first high-k gate dielectric layer is higher than an upper surface of the semiconductor substrate. The memory element also includes a first metal gate electrode layer disposed over the first high-k gate dielectric layer. A lower portion of the first metal gate electrode layer is surrounded by the first high-k gate dielectric layer, and a width of an upper portion of the first metal gate electrode layer is greater than a width of the lower portion of the first metal gate electrode layer. The memory element also includes a first dielectric portion disposed over the first metal gate electrode layer.

A transition metal dichalcogenide (TMD) transistor includes a substrate, an n-type two-dimensional (2D) TMD layer, a metal source electrode, a metal drain electrode, and a gate dielectric. The substrate has a top portion that is an insulating layer, and the n-type 2D TMD layer is on the insulating layer. The metal source electrode, the metal drain electrode, and the gate dielectric are on the n-type 2D TMD layer. The metal gate electrode is on top of the gate dielectric and is between the metal source electrode and the metal drain electrode.

The present application relates to the technical field of MOS semiconductor, and discloses a metal oxide semiconductor field effect transistor with high-K gate dielectric layer and metal gate electrode, which is composed of a plurality of mutually juxtaposed MOS cells, and each MOS cell comprises a drain, a semiconductor epitaxial layer, a source, a gate and a gate oxide layer, the gate comprises a left gate and a right gate, and the cross-sectional profile of the left gate and the right gate is in the shape of an L; a doped polysilicon is arranged between the left gate and the right gate, and the doped polysilicon is one of P-type polysilicon or N-type polysilicon. The present application increases the gate control area by the L-shaped metal gate, combines the vertical electric field gradient formed by the gradient doped polysilicon, significantly reduces the gate resistance and optimizes the carrier mobility, improves the current driving capacity by more than 20%, and at the same time, relieves the reliability problem caused by the high-K dielectric / silicon interface defects.

A memory device includes a first high-k gate dielectric layer disposed in a semiconductor substrate. A top surface of the first high-k gate dielectric layer is higher than a top surface of the semiconductor substrate. The memory device also includes a first metal gate electrode layer disposed over the first high-k gate dielectric layer. A lower portion of the first metal gate electrode layer is surrounded by the first high-k gate dielectric layer, and a width of an upper portion of the first metal gate electrode layer is greater than a width of the lower portion of the first metal gate electrode layer. The memory device further includes a first dielectric portion disposed over the first metal gate electrode layer.

This application relates to a trench field-effect transistor with a segmented gate structure and a method for manufacturing the same. The transistor includes: a substrate region, a drift region, a body region, a source region, a shielding gate, a control gate, an insulating layer, a source electrode, a drain electrode, and a metal gate electrode; the drift region, the body region, the source region, and the source electrode are sequentially disposed above the substrate region, and the drain electrode is disposed below the substrate region; the control gate and the shielding gate are sequentially disposed on one side of the drift region from top to bottom, and are respectively connected to the drift region, the body region, and the source region through the insulating layer; the control gate and the shielding gate are separated by the insulating layer; the shielding gate is composed of metal materials with different work functions from top to bottom; the control gate is composed of metal materials with different work functions from top to bottom; the source electrode is disposed above the source region; the metal gate electrode is disposed above the control gate. The solution provided by this application can improve the breakdown voltage of the transistor device.

The present invention discloses an N-type battery structure and its preparation method. The structure comprises an N-type silicon body material and a metal gate electrode formed on the surface of the N-type silicon body material. The structure is characterized in that the back surface of the N-type silicon body material is provided with a velvet surface portion and a polished surface portion, and the contact point between the metal gate electrode and the N-type silicon body material is located within the velvet surface portion. The velvet surface of the back metal gate electrode increases the contact area between the metal gate and the silicon, improving contact resistance. The flat surface of the polished area improves back-side passivation, reduces surface recombination velocity, and enhances internal reflection of long wavelengths, thereby increasing front-side current.