Semiconductor structure forming method

A semiconductor and gas technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of semiconductor structure yield to be improved, semiconductor structure performance, etc., to avoid undercutting, optimize performance, and avoid undercutting problem-solving effect
CN105097657AActive Publication Date: 2015-11-25SEMICON MFG INT (SHANGHAI) CORP
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
SEMICON MFG INT (SHANGHAI) CORP
Publication Date
2015-11-25

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Abstract

The invention relates to a semiconductor structure. A semiconductor structure forming method comprises the following steps of providing a substrate; forming a carbon-containing dielectric layer on the surface of the substrate; forming a carbon-rich protecting layer on the surface of the carbon-containing dielectric layer, wherein the carbon atom concentration in the carbon-rich protecting layer material is greater than that in the carbon-containing dielectric layer material; forming a graphical hard mask layer on the surface of the carbon-rich protecting layer; and with the graphical hard mask layer as a mask, etching the carbon-rich protecting layer and the carbon-containing dielectric layer to form an opening, wherein the opening bottom makes the substrate surface exposed; and forming a metal layer filling the opening. An undercut phenomenon is prevented. The quality of the formed metal layer is improved. The performance of the semiconductor structure is further optimized.
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Description

technical field

[0001] The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique

[0002] With the continuous progress of the VLSI process technology, the feature size of the semiconductor structure is continuously reduced, and the chip area is continuously increased. The delay time of the semiconductor structure can be compared with the device gate delay time. People are faced with the problem of how to overcome the significant increase in RC (R refers to resistance, C refers to capacitance) delay due to the rapid increase in connection length. In particular, due to the increasing influence of the capacitance between metal wiring lines, the performance of the device is greatly reduced, which has become a key restrictive factor for the further development of the semiconductor industry.

[0003] The parasitic capacitance and interconnection resistance between the ...

Claims

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