Low-power-consumption certainty BIST based on single and double jump and seed compression method thereof

A deterministic, low-power technology, applied in the direction of measuring electrical variables, measuring devices, instruments, etc., can solve problems such as failure to achieve fault coverage, high fault coverage, increased test power consumption, etc., to reduce test power consumption, Test the effect of power consumption reduction and test time reduction

Active Publication Date: 2016-07-06
厦门润积集成电路技术有限公司
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Problems solved by technology

However, compared with the deterministic test technology, the pseudo-random test technology cannot achieve the fault coverage rate that ATPG c...

Method used

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  • Low-power-consumption certainty BIST based on single and double jump and seed compression method thereof
  • Low-power-consumption certainty BIST based on single and double jump and seed compression method thereof
  • Low-power-consumption certainty BIST based on single and double jump and seed compression method thereof

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Embodiment Construction

[0030] The present invention will be further described below in conjunction with accompanying drawing.

[0031] like figure 2 As shown, a low-power deterministic BIST based on single and double transitions, including a state machine, n / 2 single and double transition units SDIC, a length of n / 2+1 bit serial shift register, a subtraction counter, Memory and circuit under test, wherein n is the test width of test vector set; Described state machine is provided with 5 input data ports, is respectively CLK, start, reset, feedback and ROM data output, in addition, state machine is also provided with 5 An output signal port is respectively SEED_BIT[n / 2-1:0], sel, ini_val, load and ROM read control signals; each SDIC unit in the n / 2 single and double transition unit SDIC is provided with 4 input ports are respectively SEED_BIT, CE, sel and clk, in addition, there are also 2 output ports, which are respectively Q1 and Q2; the length is n / 2+1 bit serial shift register, which...

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Abstract

The invention relates to the technical field of large-scale digital integrated circuits, and provides a low-power-consumption certainty BIST based on single and double jump and a seed compression method thereof. In order to reduce test power consumption, a novel single and double jump unit and an ROM control signal are applied to generate a certainty seed through single and double hybrid jump, and then certainty test vectors are generated by utilizing a single jump reseeding technology. Meanwhile, the generation number of the certainty test vectors in the reseeding process is constrained by additional arrangement of a 2-bit subtracting counter so as to reduce the number of redundant vectors and reduce test time. Besides, the corresponding seed compression method is also put forward so as to compress area overhead and generate the control signal. The experiment result proves that the test performance, such as test time, the area overhead and test power consumption, of the BIST and the seed compression method can be reduced to a large extent.

Description

technical field [0001] The invention relates to a low-power consumption deterministic BIST and a seed compression method based on single and double transitions, and belongs to the technical field of large-scale digital integrated circuits. Background technique [0002] Today, with the continuous reduction of manufacturing process dimensions and the popularization of low-power technology, the requirements for test power consumption are also increasing. In addition, the correlation between the test vectors is low, which results in much higher power consumption in the test state than in the normal working state, which will eventually affect the reliability of the chip. Therefore, how to reduce the test power consumption has become a research hotspot in recent years. At present, the research directions of low-power built-in self-test are mainly divided into two categories: (1) reducing the test power consumption of the circuit under test (2) reducing the power consumption of th...

Claims

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Application Information

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IPC IPC(8): G01R31/3187
CPCG01R31/3187
Inventor 张建伟丁秋红吴国强陈晓明滕飞马万里王政操郝文凯
Owner 厦门润积集成电路技术有限公司
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