Re-sowing test plan based on parallel folding counter

Abstract

The invention discloses a re-sowing test plan based on a parallel folding counter; the re-sowing test plan is characterized in that a test set is doubly compressed by a linear feedback shifting register (LFSR) and a folding counter code; a tested circuit moved into a multi-scan link structure in parallel by a phase shifter and a parallel folding control circuit in the test process completes the test function. In the plan of the invention, the circuit scanning structure is not changed, and the original mono-scan serial input is transformed to be multi-scan parallel input which is suitable for a plurality of test modes like random test mode, deterministic test and mixed test mode and the like; the test data storage volumes needed by tests are reduced, and the test time is greatly saved.

Description

technical field [0001] The invention relates to an integrated circuit test technology, in particular to a test data compression method in a built-in self-test (Built-InSelf-Test) method for a VLSI. Background technique [0002] The development of integrated circuit technology makes it possible to integrate hundreds of millions of devices in a chip, and can integrate pre-designed and verified IP cores, such as memory cores, microprocessor cores, DSP cores, etc. This diversified integrated chip has become an integrated system capable of processing various information, and is called a system on chip or system chip SoC. SoC greatly reduces the system cost, shortens the design cycle, and speeds up the time to market, but the testing of SoC products faces more and more challenges, such as: [0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / output p...

AI Technical Summary

Problems solved by technology

[0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / output pins of the chip, and it is difficult to directly control or observe the internal nodes of the chip through macro mechanical devices.

[0004] 2. The automatic test equipment ATE is expensive, and the development speed of chip design and manufacturing technology is faster than that of ATE. The clock frequency of the chip has exceeded the frequency of the most advanced ATE at present, and full-speed testing cannot be performed.

[0005] 3. The amount of test data is large. The more cores integrated in the SoC, the greater the amount of test data required and a sharp increase in test time

However, these solutions are incompatible with the standard scan design flow, and the structure of the scan chain needs to be reconstructed, which takes a long time and costs a lot

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