Full-covered automatic generating method of test case package of microprocessor

A technology of test cases and microprocessors, applied in software testing/debugging, detecting faulty computer hardware, functional testing, etc., can solve problems such as difficult for users to use, unable to ensure coverage of all instruction combinations, etc.

Inactive Publication Date: 2010-03-17
NAT UNIV OF DEFENSE TECH
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  • Claims
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AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is: Aiming at the problem that the random test method of the microprocessor cannot guarantee to cover all instruction combinations and the problem that the user is difficult to use, a kind of fully covered microprocessor test case package automatic generati

Method used

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  • Full-covered automatic generating method of test case package of microprocessor

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Embodiment Construction

[0045] specific implementation plan

[0046] figure 1 Is the general flowchart of the present invention.

[0047] Step 1), build the initialization function Init: form the initialization code into a separate initialization function for the test case to call;

[0048] Step 2), build the state output function Output;

[0049] Step 3), according to the description of microprocessor instruction, set up the instruction template library that comprises M instruction templates;

[0050] Step 4), the construction size is M N The set of instruction template combinations X;

[0051] Step 5), judging whether the collection X is empty, if it is empty, execute step 9), if not empty, execute step 6);

[0052] Step 6), choose an instruction template combination x to be instantiated from the set X, X=X-{x};

[0053] Step 7), instantiate each instruction template i in the instruction template combination x obtained in step 6), and obtain an instruction combination x' corresponding to x; ...

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Abstract

The invention discloses a full-covered automatic generating method of a test case package of a microprocessor, aiming to solve the problem that the formalizing method and the random testing method ofthe microprocessor can not cover all instruction combinations. The invention adopts the technical scheme that the identification, the assembling name, the source operand type and the destination operand type of each instruction are constituted into an instruction template, M instruction templates are constituted into an instruction template base with the size of M; N instruction templates are selected from the instruction template base according to instruction number N needing to be tested by users and are arranged into instruction template combinations to form MN instruction template combinations; each instruction template combination is instantiated into an instruction combination in an instantiating method; an initialization function Init, the instruction combinations and a state outputfunction Output are orderly connected into a test case, and all test cases are constituted into a test case package. The invention ensures that all test cases are covered so as to satisfy the requirements that special chip for some specific fields can not avoid omitting any function verification.

Description

technical field [0001] The invention relates to an automatic testing method for a microprocessor, in particular to a method for automatically generating a full-coverage microprocessor test case package. Background technique [0002] Accurate and rigorous testing of the functionality of a microprocessor is critical during the development of a microprocessor. The main method of functional verification is test verification based on instruction set. Due to the huge number of instruction combinations, testers manually write test cases with low efficiency and low coverage, and are generally not used as the main method. At present, automatic generation of test cases by programs is the main form of microprocessor functional testing, which can be divided into two types: formal methods and random methods. [0003] The formal method refers to the establishment of an abstract state machine model of the component to be tested, and the automatic generation of test cases by using techniq...

Claims

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Application Information

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IPC IPC(8): G06F11/36G06F11/26
Inventor 王锋杨灿群易会战陈娟黄春赵克佳杜云飞
Owner NAT UNIV OF DEFENSE TECH
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