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Method for realizing supporting of EJTAG detection in instruction grade random detection

A technology of random testing and implementation method, applied in the direction of software testing/debugging, etc., can solve the problem of inability to realize on-chip cross-debugger testing, and achieve the effect of high test efficiency, low efficiency and high efficiency

Active Publication Date: 2007-03-28
LOONGSON TECH CORP
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Problems solved by technology

[0007] The purpose of the present invention is to overcome the deficiency that the existing instruction-level random test technology cannot realize the on-chip cross-debugger test, thereby providing a method for supporting EJTAG testing in the instruction-level random test, which can effectively support cross-debugging on the chip containing EJTAG The test and verification of the microprocessor core of the processor without affecting the original performance advantages of the instruction level random test

Method used

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  • Method for realizing supporting of EJTAG detection in instruction grade random detection
  • Method for realizing supporting of EJTAG detection in instruction grade random detection
  • Method for realizing supporting of EJTAG detection in instruction grade random detection

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Embodiment Construction

[0035] Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

[0036] As shown in Figure 2, a method for supporting EJTAG testing in instruction-level random testing includes the following steps:

[0037]Step 1, add the EJTAG debugging command SDBBP / DRET in the command library;

[0038] Step 2, add constraints related to debugging instructions in the instruction template;

[0039] Step 3, improve the instruction-level random test generation engine, add access instruction judgment, program counter random extraction, access address record, access data record, jump instruction record, and add corresponding output signals at the same time;

[0040] Step 4, add the execution mechanism of the debugging instruction SDBBP / DRET in the instruction level simulator, and add the debugging control register (DCR) at the same time, and provide the correct result when the system enters the EJTAG debugging interrupt;

[00...

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Abstract

This invention discloses a method supporting EJTAG test in dictation random testing. It includes the following steps: add SDBBP / DRET dictation to the library; add corresponding restriction to the dictation stencil; generate engine to improve the random testing; add executive mechanism of SDBBP / DRET to the simulator and add debugging control register; add input / output signals and comparison logic in simulating circumstance; pre-store EJTAG debugging exceptional processing program in memorizer. This invention not only preserves advantages of traditional dictation random testing, but also supports testing and validating the debugger on the EJTAG.

Description

technical field [0001] The invention relates to microprocessor verification technology, in particular to a method for supporting Enhanced Joint Test Action Group (hereinafter referred to as EJTAG) testing in instruction-level random testing. Background technique [0002] Instruction-level random testing is a common method for general-purpose microprocessor verification. As shown in Figure 1, it usually includes five parts: instruction library 11, instruction template 12, generation engine 13, instruction-level simulator 14, and simulation environment 15. The instruction library 11 contains all effective instructions supported by the processor; the instruction template 12 is a series of configuration files for configuration, specification and filtering of instructions; the generation engine 13 can effectively support instruction generation under the constraints of configuration files; instruction-level simulation The processor 14 is the simplest reference model of the micropr...

Claims

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Application Information

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IPC IPC(8): G06F11/36
Inventor 沈海华王朋宇胡伟武
Owner LOONGSON TECH CORP
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