Code optimization method and device, electronic equipment and storage medium

Abstract

The invention provides a code optimization method and device, electronic equipment and a storage medium, and relates to the technical field of computers, in particular to the technical field of code optimization and code compiling. The specific implementation scheme of the method comprises the following steps: inserting a memory barrier code between at least two first memory access codes of each of a plurality of loop code blocks to be optimized in a code snippet to be optimized to obtain a plurality of optimized loop code blocks; the at least two first memory access codes are respectively located in at least two target code sequences in the to-be-optimized loop code block, and the at least two first memory access codes are dependent on each other; inserting a memory barrier code between the at least two second memory access codes to obtain an optimized code snippet for the to-be-optimized code snippet; the second memory access codes are respectively located in at least two loop code blocks in the to-be-optimized code snippets; the at least two loop code blocks comprise optimized loop code blocks; the at least two second memory access codes have a dependency relationship with each other.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, in particular to the field of chips, code optimization, and code compilation technology, and involves code optimization methods, devices, electronic devices, and storage media. Background Art

[0002] A memory barrier is a synchronization mechanism used to maintain the sequential nature of memory access operations in concurrent systems. To improve processor performance, execution units execute instructions out of order when possible. In a multi-core or multi-threaded concurrent environment, out-of-order instruction execution can cause memory conflicts between threads.

[0003] Therefore, there is an urgent need for a method that can accurately insert memory barrier code into the source code to maintain the order of memory access operations and avoid memory conflicts in memory access operations between threads due to the lack of memory barrier code. Summary of the Invention

[0004] The present disclosure provides a code optimization method, device, electronic device, and storage medium.

[0005] According to one aspect of the present disclosure, a code optimization method is provided, comprising: inserting a memory barrier code between at least two first memory access codes of each of a plurality of loop code blocks to be optimized in a code fragment to be optimized, to obtain a plurality of optimized loop code blocks; wherein the at least two first memory access codes are respectively located in at least two target code sequences within the loop code block to be optimized, and the at least two first memory access codes have a dependency relationship with each other; and inserting the memory barrier code between at least two second memory access codes to obtain an optimized code fragment for the code fragment to be optimized; wherein the second memory access codes are respectively located in at least two loop code blocks within the code fragment to be optimized; the at least two loop code blocks include: an optimized loop code block; and the at least two second memory access codes have a dependency relationship with each other.

[0006] According to another aspect of the present disclosure, a code optimization device is provided, comprising: a first optimization module and a second optimization module. The first optimization module is used to insert a memory barrier code between at least two first memory access codes of each of a plurality of loop code blocks to be optimized in a code fragment to be optimized, to obtain a plurality of optimized loop code blocks; wherein, at least two first memory access codes are respectively located in at least two target code sequences within the loop code block to be optimized, and at least two first memory access codes have a dependency relationship with each other. The second optimization module is used to insert a memory barrier code between at least two second memory access codes, to obtain an optimized code fragment for the code fragment to be optimized; wherein, the second memory access codes are respectively located in at least two loop code blocks within the code fragment to be optimized; at least two loop code blocks include: an optimized loop code block; at least two second memory access codes have a dependency relationship with each other.

[0007] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described above.

[0008] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the method described above.

[0009] According to another aspect of the present disclosure, a computer program product is provided, comprising a computer program, which implements the method described above when executed by a processor.

[0010] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0012] Figure 1 Schematically illustrates an exemplary system architecture to which the code optimization method and apparatus according to an embodiment of the present disclosure can be applied;

[0013] Figure 2 The following schematically shows a flow chart of a code optimization method according to an embodiment of the present disclosure;

[0014] Figure 3Schematically shows a schematic diagram of optimizing an initial loop code block according to an embodiment of the present disclosure;

[0015] Figure 4A Schematically illustrates a schematic diagram of determining a memory barrier code insertion position for an initial code sequence according to an embodiment of the present disclosure;

[0016] Figure 4B Schematically illustrating a schematic diagram of determining a memory barrier code insertion position for an initial code sequence according to another embodiment of the present disclosure;

[0017] Figure 5 Schematically shows a schematic diagram of inserting memory barrier codes between target code sequences within a loop code block to be optimized according to an embodiment of the present disclosure;

[0018] Figure 6 Schematically shows a schematic diagram of inserting memory barrier codes between different loop code blocks according to an embodiment of the present disclosure;

[0019] Figure 7 A block diagram schematically shows a code optimization device according to an embodiment of the present disclosure; and

[0020] Figure 8 A block diagram of an electronic device suitable for implementing a code optimization method according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0021] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0022] When writing program source code, operator developers manually insert memory barrier code between memory access codes that could cause memory conflicts. However, due to the large amount of source code and complex logic, memory barrier code can be omitted or incorrectly inserted in the source code, leading to errors during the execution of executable programs compiled from this source code.

[0023] In view of this, the embodiment of the present disclosure reduces the problem of missed or incorrect insertion of memory barrier codes by inserting memory barrier codes respectively for the first memory access code with a dependency relationship within the loop code block and for the second memory access code with a dependency relationship between the loop code blocks, further improves the accuracy of memory barrier code insertion, and avoids memory conflicts in memory access operations between threads due to the lack of memory barrier codes.

[0024] Figure 1 An exemplary system architecture to which the code optimization method and apparatus according to an embodiment of the present disclosure can be applied is schematically shown.

[0025] It should be noted that Figure 1 The examples shown are merely examples of system architectures to which the embodiments of the present disclosure may be applied, to help those skilled in the art understand the technical content of the present disclosure. This does not mean that the embodiments of the present disclosure cannot be applied to other devices, systems, environments, or scenarios. For example, in another embodiment, an exemplary system architecture to which the code optimization method and apparatus may be applied may include a terminal device, but the terminal device may implement the code optimization method and apparatus provided by the embodiments of the present disclosure without interacting with a server.

[0026] like Figure 1 As shown, the exemplary architecture 100 may include a compiler 1100 , which may include an optimization module 1111 and a compilation module 1112 .

[0027] In the embodiment of the present disclosure, the source code can be input into the optimization module 1111, and the optimization module 1111 executes the code optimization method provided by the embodiment of the present disclosure to optimize the code fragment 110 to be optimized in the source code, respectively, within the loop code block and between the loop code blocks, to generate optimized code.

[0028] For example: First, perform the optimization operations within the loop code block, such as Figure 1 103. As shown in FIG. 104 , the optimized loop code block B1101 to be optimized in the code snippet 110 may include at least memory access code L11011, memory access code S11012, and memory access code S21013. The memory access code L11011 and the memory access code S11012 have the same subscript, indicating that the memory access code L11011 and the memory access code S11012 will access the same memory address during program execution. L can represent a Load operation, and S can represent a Store operation. Since the memory access code L11011 and the memory access code S11012 access the same memory address and have different types of memory access operations, it can be determined that there is a dependency relationship between the memory access code L11011 and the memory access code S11012. Therefore, the memory barrier code 130 can be inserted before the memory access code S11012 to obtain the optimized loop code block B2103. This ensures that during program execution, the memory access code S11012 needs to wait until the memory access code L11011 is completed before execution.

[0029] For example: Then, perform optimization operations between loop code blocks, such as Figure 1As shown in the code snippet to be optimized 120 in the optimized loop code block B2103, since there is data dependency between the memory access code S21013 in the optimized loop code block B2103 and the memory access code L21021 in the loop code block B3102, the memory barrier code 130 can be inserted before the memory access code L21021 to generate the optimized code.

[0030] Finally, the compilation module 1112 compiles the optimized code and outputs an executable program.

[0031] Figure 2 The flowchart of the code optimization method according to the embodiment of the present disclosure is schematically shown.

[0032] like Figure 2 As shown, the method includes operations S210 to S220.

[0033] In operation S210 , a memory barrier code is inserted between at least two first memory access codes of each of a plurality of loop code blocks to be optimized in the code segment to be optimized, to obtain a plurality of optimized loop code blocks.

[0034] According to an embodiment of the present disclosure, a code segment to be optimized may be a code segment to be optimized in a source code. The code segment to be optimized may include multiple loop code blocks to be optimized. The loop code block to be optimized may represent a loop code block having at least two first memory access codes that are data dependent on each other. The at least two first memory access codes are respectively located in at least two target code sequences within the loop code block to be optimized.

[0035] For example: the code fragment to be optimized may include the loop code block B to be optimized 01 , loop code block B to be optimized 01 The target code sequence Se1 and the target code sequence Se2 may be included. The access code S in the target code sequence Se1 01 The memory access code L in the target code sequence Se2 01 There is a dependency relationship between the two, which can determine the access code S 01 and access code L 01 is the first access code, and in the access code S 01 and access code L 01 Insert memory barrier code between to generate optimized loop code block B 02 .

[0036] In some embodiments, the target code sequence may be a continuously executed code sequence, and memory barrier codes may have been inserted between memory access codes that have dependencies on each other in the target code sequence.

[0037] In operation S220 , a memory barrier code is inserted between at least two second memory access codes to obtain an optimized code segment for the code segment to be optimized.

[0038] According to an embodiment of the present disclosure, the second memory access code is respectively located in at least two loop code blocks within the code segment to be optimized. The at least two loop code blocks may include an optimized loop code block. The at least two second memory access codes are dependent on each other.

[0039] In some embodiments, at least two loop code blocks may be optimized loop code blocks. For example: the optimized loop code block B 02 Access code S in 02 And the optimized loop code block B 03 The access code L in 02 There is a dependency relationship between them, which can determine the access code S 02 and access code L 02 For the second access code. And in the access code S 02 and access code L 02 Insert memory barrier code between them to generate optimized code snippets.

[0040] In some embodiments, the at least two loop code blocks may include an optimized loop code block and a loop code block that does not require optimization. The loop code block that does not require optimization may indicate that memory access codes within the loop code block have no dependencies with each other.

[0041] For example: Optimized loop code block B 04 Access code S in 03 and the memory access code L in the loop code block that does not need to be optimized 03 There is a dependency relationship between them, which can determine the access code S 03 and access code L 03 For the second access code. And in the access code S 03 and access code L 03 Insert memory barrier code between them to generate optimized code snippets.

[0042] The disclosed embodiment reduces the problems of missed or incorrect insertion of memory barrier codes by inserting memory barrier codes into the first memory access code with dependencies within the loop code block and into the second memory access code with dependencies between the loop code blocks, further improves the accuracy of memory barrier code insertion, and avoids memory conflicts in memory access operations between threads due to missing memory barrier codes.

[0043] To further reduce the probability of memory barrier code insertion errors, the code optimization method provided in the embodiments of the present disclosure may further include the following operation: inserting memory barrier code between at least two third memory access codes in each of multiple consecutively executed initial code sequences of an initial loop code block, thereby obtaining multiple target code sequences for the loop code block to be optimized. The third memory access codes are located in the consecutively executed initial code sequences, and at least two of the third memory access codes have a dependency relationship with each other.

[0044] According to an embodiment of the present disclosure, the source code may include multiple initial code segments, each of which may include at least one initial loop code block, wherein the initial loop code block may include multiple continuously executed initial code sequences.

[0045] Figure 3 The figure schematically shows a schematic diagram of optimizing an initial loop code block according to an embodiment of the present disclosure.

[0046] like Figure 3 As shown, this embodiment 300 may include an initial code segment 310, which may include an initial loop code block B0 311 and a loop code block B4 312. The initial loop code block B0 311 may include an initial code sequence Se0 3111. The initial code sequence Se0 3111 may include memory access code S3301 and memory access code L3302. There is a dependency relationship between memory access code S3301 and memory access code L3302. Therefore, memory access code S3301 and memory access code L3302 may be determined as the third memory access code. Memory barrier code 303 is inserted between memory access code S3301 and memory access code L3302 to generate a target code sequence Se1 3211. At this point, the optimized initial loop code block B0 may be the loop code block to be optimized B3321, and the optimized initial code segment may be the code segment to be optimized 320.

[0047] Then, based on the dependency relationship between the memory access codes in the loop code block B3321 to be optimized and the loop code block B3321 to be optimized and the loop code block B4 in the code segment to be optimized 320, the following can be used: Figure 1 The described method performs optimization within a loop code block and optimization between loop code blocks respectively, and finally generates optimized code fragments.

[0048] like Figure 3 As shown, in the loop code block B3321 to be optimized, there is a dependency relationship between the memory access code L43112 and the memory access code S43113. The memory barrier code 303 can be inserted between the memory access code L43112 and the memory access code S43113 to generate an optimized loop code block.

[0049] like Figure 3As shown, there is a dependency relationship between the memory access code S73114 in the optimized loop code block and the memory access code L73121 in the loop code block B4312. The memory barrier code 303 can be inserted between the memory access code S73114 and the memory access code L73121 to generate an optimized code snippet.

[0050] The continuously executed initial code sequence in the initial loop code block is used as the minimum unit for inserting memory barrier code, and then the insertion operation is gradually performed within the loop code block and between the loop code blocks, which further reduces the probability of memory barrier code insertion errors and improves the efficiency of code optimization.

[0051] The initial code sequence may include a plurality of third memory access codes that are dependent on each other. When the memory barrier code insertion operation is performed on the initial code sequence, the insertion operation may be performed in an iterative manner.

[0052] According to an embodiment of the present disclosure, inserting a memory barrier code between at least two third memory access codes of each of multiple continuously executed initial code sequences of an initial loop code block to obtain multiple target code sequences of the loop code block to be optimized can include the following operations: determining a target position for the memory barrier code in the initial code sequence; generating an intermediate code sequence by inserting the memory barrier code at the target position; generating a target code sequence by inserting the memory barrier code between the at least two fourth memory access codes in response to determining that there is a dependency relationship between at least two fourth memory access codes in the intermediate code sequence; and determining that the intermediate code sequence is a target code sequence in response to determining that there is no dependency relationship between any at least two fourth memory access codes in the intermediate code sequence.

[0053] In some embodiments, the initial code sequence may include multiple memory access codes. By sequentially traversing each memory access code, N pairs of third memory access codes having a dependency relationship with each other are determined, where N can be an integer greater than 1. A memory barrier code can then be inserted into the nth pair of third memory access codes to obtain an intermediate code sequence. In the intermediate code sequence, if at least two fourth memory access codes having a dependency relationship still exist in the memory access code following the memory barrier code, the memory barrier code is inserted between the at least two fourth memory access codes until no two fourth access codes in the intermediate code sequence have a dependency relationship with each other, thereby obtaining a target code sequence.

[0054] Through iterative loops, each pair of memory access codes that have dependencies on each other in the initial code sequence is judged in turn until there is no dependency between any two memory access codes, and the target code sequence is obtained, which further improves the accuracy of the memory barrier code insertion position and reduces the probability of insertion errors and insertion omissions.

[0055] After the memory barrier code is inserted, all memory access codes following the memory barrier code must wait for the memory access code preceding the memory barrier code to complete execution before they can execute. Therefore, when inserting the memory barrier code, the insertion position of the memory barrier code between the first memory access codes can be determined, taking into full consideration the impact of the memory barrier code insertion on the execution time of the entire code sequence, thereby reducing the impact of the memory barrier code insertion on the execution time of the entire code sequence.

[0056] The following combination Figure 4A and Figure 4B An embodiment of determining a memory barrier code insertion position for an initial code sequence is described in detail.

[0057] In some embodiments, the initial code sequence further includes a plurality of code groups located between the at least two third memory access codes, the plurality of code groups including non-memory access codes.

[0058] According to an embodiment of the present disclosure, determining a target position for a memory barrier code in an initial code sequence may include the following operations: determining a first position of at least two third memory access codes in the initial code sequence; and determining a position adjacent to the first position as a target position along a first predetermined direction.

[0059] Figure 4A The diagram schematically shows a method for determining a memory barrier code insertion position for an initial code sequence according to an embodiment of the present disclosure.

[0060] like Figure 4A As shown, in the initial code sequence Se03111A, the memory access code S3301 and the memory access code L3302 are dependent on each other, and it can be determined that the memory access code S3301 and the memory access code L3302 are the third memory access code.

[0061] There are multiple code groups between the memory access code S3301 and the memory access code L3302, and the multiple code groups may include: non-memory access code C13011, non-memory access code Ci 301i, ..., non-memory access code Cn301n.

[0062] In the embodiment of the present disclosure, the first predetermined direction may be opposite to the direction of the execution order of each code in the initial code sequence. For example, if the execution order of each code is from top to bottom, the first predetermined direction is from bottom to top.

[0063] In the embodiment of the present disclosure, first, the first positions of the memory access code S3301 and the memory access code L3302 in the initial code sequence can be determined. Then, the position adjacent to the first position can be determined along the bottom-to-top direction, and the adjacent position can be a position before the first position. Since the position adjacent to the first position of the memory access code S3301 along the bottom-to-top direction can be a position before the first position of the memory access code S3301, it has exceeded the position interval range between the memory access code S3301 and the memory access code L3302. Therefore, the position adjacent to the first position of the memory access code S3301 can be excluded. The position adjacent to the first position of the memory access code L3302 is within the position interval range between the memory access code S3301 and the memory access code L3302. Therefore, the position adjacent to the first position of the memory access code L3302 can be determined as the target position.

[0064] Since the memory access code S3301 and the memory access code L3302 are dependent on each other, the memory access code L3302 needs to be executed after the memory access code S3301 is executed.

[0065] In such Figure 4A In the embodiment shown, the memory access code S3301 and the memory access code L3302 are all non-memory access codes. When these non-memory access codes are executed, they will not perform memory access operations on the memory. Therefore, the memory barrier code can be directly inserted before the memory access code L3302 to ensure that the memory access code S3301 has been executed when the memory access code L3302 is executed.

[0066] Even if the execution time of the memory access code S3301 is longer than the total execution time of the non-memory access code C13011, the non-memory access code Ci 301i, ..., and the non-memory access code Cn301n, due to the insertion of the memory barrier code, it is still necessary to wait until the execution of the memory access code S3301 is completed before executing the memory access code L3302.

[0067] Therefore, the memory barrier code 303 can be inserted before the memory access code L3302 to generate the target code sequence Se13211A.

[0068] In some embodiments, the initial code sequence further includes multiple code groups located between at least two third memory access codes, the multiple code groups including non-memory access codes and at least one fifth memory access code. There is no dependency relationship between the third memory access code and the fifth memory access code.

[0069] Figure 4B The following schematically illustrates a diagram of determining a memory barrier code insertion position for an initial code sequence according to another embodiment of the present disclosure.

[0070] like Figure 4BAs shown, in the initial code sequence Se03111B, the memory access code S3301 and the memory access code L3302 are dependent on each other, and it can be determined that the memory access code S3301 and the memory access code L3302 are the third memory access code.

[0071] There are multiple code groups between the memory access code S3301 and the memory access code L3302. The multiple code groups may include: non-memory access code C13011, memory access code S0 301j and non-memory access code Cn301n.

[0072] Since the memory access code S0 301j needs to perform memory access operations when it is executed, if the memory barrier code is directly inserted before the memory access code L3302, it means that the memory access code L3302 not only needs to wait for the completion of the memory access code S3301, but also needs to wait for the completion of the memory access code S0 301j. However, the memory address accessed when the memory access code S0 301j is executed does not conflict with the memory access code L3302. Therefore, if the memory barrier code is directly inserted before the memory access code L3302, the memory access code L3302 may need to wait additionally for the completion of the memory access code S0 301j, thereby reducing the code execution efficiency.

[0073] Therefore, according to an embodiment of the present disclosure, determining the target position for the memory barrier code in the initial code sequence may include the following operations: obtaining a first execution time required for each target memory access code in the initial code sequence to be executed and a second execution time required for each non-memory access code to be executed to be executed; obtaining multiple estimated waiting times for multiple candidate positions based on the first execution time and the second execution time; and determining the target position from multiple candidate positions based on the multiple estimated waiting times.

[0074] In the embodiment of the present disclosure, the target memory access code includes a third memory access code and at least one fifth memory access code.

[0075] In some embodiments, first, a first execution duration can be simulated using a simulated hardware execution program model based on the parameters of the hardware environment used to run the code snippet to be optimized and the type of target memory access code. Similarly, a second execution duration can be simulated using a simulated hardware execution program model based on the parameters of the hardware environment used to run the code snippet to be optimized and the type of non-memory access code.

[0076] Then, if Figure 4BAs shown, for candidate position Po1410, the estimated waiting time for candidate position Po1410 can be calculated based on the first execution time of memory access code S3301 and the second execution time of non-memory access code C13011. For candidate position Po2420, the estimated waiting time for candidate position Po2420 can be calculated based on the first execution time of memory access code S3301 and memory access code S0 301j and the second execution time of non-memory access code C13011 and non-memory access code Cn301n.

[0077] Finally, the candidate location with the shortest expected waiting time can be determined as the target location. A waiting time threshold can also be configured based on the actual application scenario, and the candidate location with a waiting time less than or equal to the threshold can be determined as the target location.

[0078] like Figure 4B As shown, when the candidate position Po1 is determined to be the target position, the memory barrier code 303 is inserted between the non-memory access code C13011 and the memory access code S0 30lj to generate a target code sequence Se13211B, indicating that the memory access code L3302 only needs to wait for the memory access code S3 to be executed before it can be executed.

[0079] By fully considering the impact of the memory barrier code insertion on the execution time of the entire code sequence, the insertion position of the memory barrier code between the first memory access codes is determined, thereby reducing the impact of the memory barrier code insertion on the execution time of the entire code sequence and further improving the code execution efficiency.

[0080] In the embodiment of the present disclosure, the expected waiting time of the candidate position may be defined as the maximum value of the expected waiting times of a plurality of target memory access codes located before the candidate position.

[0081] According to an embodiment of the present disclosure, multiple expected waiting times for multiple candidate positions are obtained respectively according to the first execution time and the second execution time, which may include the following operations: according to the first execution time and the second execution time, respectively calculating the expected waiting time of multiple target memory access codes located before the multiple candidate positions; in the initial code sequence, determining the maximum value of the expected waiting time of each of the multiple target memory access codes located before the first candidate position as the first expected waiting time for the first candidate position; in the initial code sequence, determining the maximum value of the expected waiting time of each of the multiple target memory access codes located before the second candidate position as the second expected waiting time for the second candidate position; in response to determining that the first expected waiting time is less than or equal to the second expected waiting time, determining the first candidate position as the target position; and in response to determining that the first expected waiting time is greater than the second expected waiting time, determining the second candidate position as the target position.

[0082] In some embodiments, the first candidate position may be a position before any fifth memory access code and adjacent to any fifth memory access code, and the second candidate position may be a position before the third memory access code and between two third memory access codes that have a dependency relationship with each other.

[0083] like Figure 4B As shown, the first candidate position may be candidate position Po1410. For candidate position Po1410, since the target memory access code at candidate position Po1410 only includes memory access code S3301, the estimated waiting time of memory access code S3301 may be used as the first estimated waiting time for candidate position Po1410. The second candidate position may be candidate position Po2420. For candidate position Po2420, since the target memory access code at candidate position Po2420 includes memory access code S3301 and memory access code S0 301j, the maximum estimated waiting time of memory access code S3301 and memory access code S0 301j may be determined as the second estimated waiting time for candidate position Po2420.

[0084] In an embodiment of the present disclosure, the expected waiting time of each of the multiple target memory access codes located before the multiple candidate positions is calculated based on the first execution time and the second execution time, which may include the following operations: for each target memory access code, the sum of the time required for the execution of multiple code groups located after the target memory access code in the initial code sequence is determined as the idle time of each target memory access code; and the expected waiting time of each target memory access code is obtained based on the execution time required for the execution of each target memory access code and the idle time of each target memory access code.

[0085] In some embodiments, according to the requirements of actual application scenarios and based on various mathematical methods, the estimated waiting time of each target memory access code can be obtained according to the execution time required for each target memory access code to be executed and the idle time of each target memory access code.

[0086] In some embodiments, the difference between the execution time required to complete execution of each target memory access code and the idle time of each target memory access code can be determined as the expected waiting time of each target memory access code.

[0087] For example: the idle time of memory access code S3301 = the second execution time of non-memory access code C13011 + the first execution time of memory access code S0301j + the first execution time of non-memory access code C n The second execution time of 301n. The expected waiting time of the memory access code S3301 = the first execution time of the memory access code S3301 - the idle time of the memory access code S3301.

[0088] In some embodiments, a waiting coefficient can be determined by calculating the ratio of the difference between the execution time required for each target memory access code to complete execution and the idle time of each target memory access code, and the idle time of each target memory access code. The product of the waiting coefficient and a preset time is then used to determine the expected waiting time for each target memory access code. The preset time can be a reference time preconfigured based on the requirements of an actual application scenario.

[0089] For example: the idle time of memory access code S0 301j = non-memory access code C n The estimated waiting time of the memory access code S0 301j = the preset time × (the first execution time of the memory access code S0 301j - the idle time of the memory access code S0 301j) / the idle time of the memory access code S0 301j.

[0090] According to an embodiment of the present disclosure, based on the positional relationship between each target memory access code and other target memory access codes and non-memory access codes in the initial code sequence, the expected waiting time that may be generated by each target memory access code during execution is calculated respectively, so as to accurately determine the position for inserting the memory barrier code, thereby further improving the code execution efficiency.

[0091] The initial code sequence serves as the smallest unit to be optimized within the code fragment to be optimized. By calculating the expected waiting time of each target memory access code separately, the additional waiting overhead caused by the insertion of the memory barrier code on the fifth memory access code that has no dependency on the third memory access code is reduced.

[0092] After optimizing the initial code sequence to obtain the target code sequence, there are still memory access codes with dependencies between the target code sequences. For example, a first memory access code located within the loop code block to be optimized and a second memory access code located between the optimized loop code block and the unoptimized loop code block.

[0093] The following will be combined Figure 5 and Figure 6 Describes in detail the optimization process within and between loop code blocks.

[0094] Since the logical relationship in the code fragment to be optimized is relatively complex, in order to improve the insertion accuracy of the memory barrier code, the memory barrier code is inserted between at least two first memory access codes of each of the multiple loop code blocks to be optimized in the code fragment to be optimized to obtain multiple optimized loop code blocks, which may include the following operations: generating a first set of codes to be verified for each target code sequence based on the execution logic between the multiple target code sequences in the loop code block to be optimized and the position of the memory shielding code in each target code sequence; and in response to determining that there is a dependency relationship between the candidate memory access code in the first set of codes to be verified and the candidate memory access code in the first target code sequence among the multiple target codes, taking the candidate memory access code as the first memory access code, and inserting the memory barrier code in the first target code sequence.

[0095] In an embodiment of the present disclosure, the first set of codes to be verified may be included in the loop code block to be optimized, in all target execution sequences before executing the target execution sequence Se1, and in all memory access codes that are not shielded by memory barrier codes during the execution of the target execution sequence Se1.

[0096] Figure 5 The diagram schematically shows a schematic diagram of inserting memory barrier codes between target code sequences within a loop code block to be optimized according to an embodiment of the present disclosure.

[0097] like Figure 5 As shown, the loop code block 321 to be optimized may include a target code sequence Se1510, a target code sequence Se2520, a target code sequence Se3530 and a target code sequence Se4540. Figure 5 The arrows in the figure indicate the execution order between target code sequences.

[0098] In some embodiments, generating a first set of codes to be verified for each target code sequence based on the execution logic between each target code sequence within the loop code block to be optimized and the position of the memory shielding instruction in each target code sequence can include the following operations: determining a first execution order between each target code sequence based on the execution logic between each target code sequence within the loop code block to be optimized; determining the memory access code located after the memory shielding code as the first set of codes to be verified in response to determining that the target code sequence executed first contains the memory shielding code according to the first execution order; and determining the memory access code in the target code sequence executed first contains the memory shielding instruction according to the first execution order.

[0099] like Figure 5 As shown, the target code sequence executed first relative to the target code sequence Se2520 is the target code sequence Se1510.

[0100] First, in the target code sequence Se1 510, the memory access code S3 511 has been blocked by the memory barrier code 512. Therefore, the memory access code L3 513 following the memory barrier code 512 in the target code sequence Se1 510 can be determined as a candidate memory access code in the to-be-verified code set G1 5201. Similarly, the memory access code L3 513 can also be determined as a candidate memory access code in the to-be-verified code set G2 5301.

[0101] Then, along the direction of the arrow, the target code sequences executed previously relative to the target code sequence Se4540 include: target code sequence Se2520 and target code sequence Se3530.

[0102] Since there is no memory barrier code in the target code sequence Se2520, the memory access code S4521 and the memory access code S5522 in the target code sequence Se2520, and the memory access code L3513 in the code set to be verified G15201 can all be determined as candidate memory access codes for the code set to be verified G3.

[0103] Since the target code sequence Se3530 contains a memory barrier code, the memory access code L6533 following the memory barrier code in the target code sequence Se3530 can also be determined as a candidate memory access code of the to-be-verified code set G3.

[0104] Next, based on the candidate memory access codes in the to-be-verified code set corresponding to each target code sequence, dependency verification is performed one by one on the candidate memory access codes in each target code sequence.

[0105] For example: For the memory access code S6531 and memory access code L6533 in the target code sequence Se3530, and the memory access code L3513 in the code set to be verified G25301, it can be seen that the memory access code L3513 and the memory access code S6531 have different subscripts and do not access the same memory address. Therefore, it can be determined that there is no dependency between the memory access code L3513 and the memory access code S6531. Similarly, it can also be determined that there is no dependency between the memory access code L6533 and the memory access code L3513. Therefore, it can be determined that there is no need to insert a memory barrier code between the target code sequence Se3530 and the target code sequence Se1510. It can be understood that if the subscripts of multiple memory access codes are different, it means that the multiple memory access codes will access different addresses.

[0106] For another example, a dependency check is performed on memory access code L5541 and memory access code L7542 in the target code sequence Se4540, and the candidate codes in the code set to be verified G3 5401. Since memory access code S5522 and memory access code L5541 have the same subscript and different memory access operation types, it can be determined that a dependency relationship exists between memory access code S5522 and memory access code L5541. Memory barrier code 501 can be inserted before memory access code L5541 in the target code sequence Se4 to generate an optimized loop code block. It can be understood that if multiple memory access codes have the same subscript, it means that the multiple memory access codes will access the same address.

[0107] By following the logical execution order between the target code sequences within the loop code block to be optimized, dependency checks are performed one by one on each memory access code in the target execution sequence and all memory access codes in all previously executed target execution sequences that were not shielded by the memory barrier code during the execution of the target execution sequence, to determine whether the memory barrier code needs to be inserted, thereby reducing the accuracy of the memory barrier code insertion position.

[0108] After the loop code block is optimized, the code segment to be optimized may still contain a second memory access code that has a dependency relationship between the optimized loop code block and other loop code blocks.

[0109] Therefore, according to an embodiment of the present disclosure, inserting a memory barrier code between at least two second memory access codes to obtain an optimized code fragment for the code fragment to be optimized may include the following operations: generating a second set of codes to be verified for each target code sequence based on the execution logic between multiple optimized loop code blocks within the code fragment to be optimized and the position of the memory barrier code in each loop code block; and inserting a memory barrier code into the second target code sequence in response to determining that there is a dependency relationship between a candidate memory access code in the second set of codes to be verified and a candidate memory access code in a second target code sequence among the multiple target code sequences.

[0110] In an embodiment of the present disclosure, the second set of codes to be verified may include all memory access codes that are not shielded by memory barrier codes during the execution of the target execution sequence Se1 in all target execution sequences before the execution of the target execution sequence Se1 between the loop code blocks.

[0111] Figure 6 The figure schematically shows a schematic diagram of inserting memory barrier codes between different loop code blocks according to an embodiment of the present disclosure.

[0112] like Figure 6As shown, the code fragment to be optimized 320 may include the optimized loop code block B3610 and the loop code block B4312. The optimized loop code block B3610 may include: target code sequence Se1510, target code sequence Se2520, target code sequence Se3530, memory barrier code 501, and target code sequence Se4540. The memory barrier code 501 is located between the target code sequence Se3530 and the target code sequence Se4540.

[0113] Figure 6 The arrow direction in indicates the execution order between each loop code block. Along the arrow direction, it can be determined that the loop code block B4312 is executed after the optimized loop code block B3610.

[0114] In an embodiment of the present disclosure, a second set of codes to be verified is generated for each target code sequence based on the execution logic between each loop code block in the code fragment to be optimized and the position of the memory barrier code in each loop code block, which may include the following operations: determining a second execution order between each loop code block based on the execution logic between each loop code block; according to the second execution order, in response to determining that there is a memory shielding code in the first executed loop code block, determining the memory access code located after the memory shielding instruction as the second set of codes to be verified; and according to the second execution order, in response to determining that there is no memory shielding code in the first executed loop code block, determining the memory access code in the first executed loop code block as the second set of codes to be verified.

[0115] like Figure 6 As shown, due to the optimized loop code block B3610, there is only the target code sequence Se4540 after the memory barrier code 501. Figure 5 It can be seen that the target code sequence Se4540 includes memory access code L5541 and memory access code L7542.

[0116] Therefore, it can be determined that the memory access code L5541 and the memory access code L7542 are candidate memory access codes in the to-be-verified code set G4 6101 .

[0117] Then, based on the candidate memory access codes in the code set to be verified G4 6101, the dependency relationship between memory access code S73121 and memory access code S83122 in loop code block B4312 is determined one by one. Because memory access code S73121 in loop code block B4312 has a dependency relationship with memory access code L7542 in the code set to be verified G4 6101, memory barrier code 303 can be inserted before memory access code L7542 to generate an optimized code snippet.

[0118] In an embodiment of the present disclosure, when inserting memory barrier code within a loop code block and between loop code blocks, the position for inserting the memory barrier code within the loop code block and between the loop code blocks can also be determined based on the method for determining the memory barrier code insertion position in the initial code sequence.

[0119] For example, when there is a fifth memory access code between memory access code L7 and memory access code S7, the position before the fifth memory access code and the position before memory access code S7 can be determined as candidate positions, and the target position can be determined by calculating the expected waiting time of each candidate position.

[0120] By checking the dependency relationship of each memory access code in the target execution sequence and all memory access codes in all previously executed target execution sequences that are not shielded by the memory barrier code during the execution of the target execution sequence according to the logical execution order between the loop code blocks, to determine whether the memory barrier code needs to be inserted, the accuracy of the memory barrier code insertion position is reduced.

[0121] Figure 7 The block diagram of the code optimization device according to the embodiment of the present disclosure is schematically shown.

[0122] like Figure 7 As shown, the code optimization device 700 may include a first optimization module 710 and a second optimization module 720 .

[0123] The first optimization module 710 is configured to insert a memory barrier code between at least two first memory access codes in each of a plurality of loop code blocks to be optimized in a code segment to be optimized, thereby obtaining a plurality of optimized loop code blocks; wherein the at least two first memory access codes are respectively located in at least two target code sequences within the loop code block to be optimized, and the at least two first memory access codes are dependent on each other.

[0124] The second optimization module 720 is used to insert a memory barrier code between at least two second memory access codes to obtain an optimized code fragment for the code fragment to be optimized; wherein the second memory access codes are respectively located in at least two loop code blocks within the code fragment to be optimized; the at least two loop code blocks include: the optimized loop code block; and there is a dependency relationship between the at least two second memory access codes.

[0125] According to an embodiment of the present disclosure, the above-mentioned device also includes a third optimization module, which is used to insert memory barrier code between at least two third memory access codes of each of multiple continuously executed initial code sequences of the initial loop code block to obtain multiple target code sequences of the loop code block to be optimized, wherein the third memory access code is located in the continuously executed initial code sequence, and at least two third memory access codes have a dependency relationship with each other.

[0126] According to an embodiment of the present disclosure, the third optimization module includes: a first determination submodule, a first generation submodule, a second generation submodule, and a second determination submodule.

[0127] The first determining submodule is configured to determine a target location for the memory barrier code in the initial code sequence.

[0128] The first generating submodule is used to generate an intermediate code sequence by inserting a memory barrier code at a target position.

[0129] The second generating submodule is configured to generate a target code sequence by inserting a memory barrier code between the at least two fourth memory access codes in response to determining that there is a dependency relationship between the at least two fourth memory access codes in the intermediate code sequence.

[0130] The second determining submodule is configured to determine that the intermediate code sequence is a target code sequence in response to determining that there is no dependency relationship between any at least two fourth memory access codes in the intermediate code sequence.

[0131] According to an embodiment of the present disclosure, the initial code sequence further includes a plurality of code groups located between at least two third memory access codes, and the plurality of code groups include non-memory access codes.

[0132] The first determination submodule may include a first determination unit configured to determine a first position of at least two third memory access codes in the initial code sequence and a second determination unit configured to determine a position adjacent to the first position along a first predetermined direction as a target position.

[0133] According to an embodiment of the present disclosure, the initial code sequence further includes a plurality of code groups located between at least two third memory access codes, the plurality of code groups including non-memory access codes and at least one fifth memory access code.

[0134] The first determining submodule may include: an acquiring unit, a calculating unit, and a third determining unit.

[0135] The acquisition unit is used to acquire a first execution time required for each target memory access code in the initial code sequence to be executed and a second execution time required for each non-memory access code to be executed; the target memory access code includes a third memory access code and at least one fifth memory access code.

[0136] The calculation unit is used to obtain a plurality of estimated waiting times for a plurality of candidate positions according to the first execution time and the second execution time.

[0137] The third determining unit is configured to determine a target location from a plurality of candidate locations based on a plurality of estimated waiting times.

[0138] According to an embodiment of the present disclosure, the plurality of candidate positions include a first candidate position adjacent to the third memory access code along the first predetermined direction and a second candidate position adjacent to the target memory access code along the first predetermined direction.

[0139] The calculation unit includes: a first calculation subunit, a first determination subunit, a second determination subunit, a third determination subunit and a fourth determination subunit.

[0140] The first calculation subunit is configured to calculate, according to the first execution time and the second execution time, respectively an estimated waiting time of each of a plurality of target memory access codes located before the plurality of candidate positions.

[0141] The first determining subunit is configured to determine, in the initial code sequence, a maximum value of respective expected waiting times of a plurality of target memory access codes located before the first candidate position as a first expected waiting time for the first candidate position.

[0142] The second determining subunit is configured to determine, in the initial code sequence, a maximum value of respective expected waiting times of a plurality of target memory access codes located before the second candidate position as a second expected waiting time for the second candidate position.

[0143] The third determining subunit is configured to determine the first candidate position as the target position in response to determining that the first estimated waiting time is less than or equal to the second estimated waiting time.

[0144] The fourth determining subunit is configured to determine the second candidate location as the target location in response to determining that the first estimated waiting time is greater than the second estimated waiting time.

[0145] According to an embodiment of the present disclosure, the first computing sub-unit is used to determine, for each target memory access code, the sum of the execution times required for multiple code groups located after the target memory access code in the initial code sequence as the idle time of each target memory access code; and to obtain the expected waiting time of each target memory access code based on the execution time required for the execution of each target memory access code and the idle time of each target memory access code.

[0146] According to an embodiment of the present disclosure, the first optimization module includes: a first set determination submodule and a first insertion submodule.

[0147] The first set determination submodule is used to generate a first code set to be verified for each target code sequence according to the execution logic between multiple target code sequences in the loop code block to be optimized and the position of the memory shielding code in each target code sequence.

[0148] The first insertion submodule is used to, in response to determining that there is a dependency relationship between a candidate memory access code in the first set of codes to be verified and a candidate memory access code in a first target code sequence among multiple target codes, use the candidate memory access code as the first memory access code and insert a memory barrier code into the first target code sequence.

[0149] According to an embodiment of the present disclosure, the first set determination submodule includes: a first order determination submodule, a first set determination submodule, and a second set determination submodule.

[0150] The first order determination submodule is used to determine a first execution order between target code sequences according to the execution logic between target code sequences in the loop code block to be optimized.

[0151] The first set determination submodule is configured to determine, in accordance with the first execution order, memory access codes following the memory shielding code as a first set of codes to be verified in response to determining that the previously executed target code sequence contains the memory shielding code.

[0152] The second set determination submodule is configured to determine, in accordance with the first execution order, memory access codes in the previously executed target code sequence as a first code set to be verified in response to determining that the previously executed target code sequence does not have a memory shielding instruction.

[0153] According to an embodiment of the present disclosure, the second optimization module includes: a second set determination submodule and a second insertion submodule.

[0154] The second set determination submodule is used to generate a second set of codes to be verified for each target code sequence according to the execution logic between multiple optimized loop code blocks in the code fragment to be optimized and the position of the memory barrier code in each loop code block.

[0155] The second insertion submodule is configured to insert a memory barrier code into the second target code sequence in response to determining that a dependency relationship exists between a candidate memory access code in the second to-be-verified code set and a candidate memory access code in a second target code sequence among the plurality of target code sequences.

[0156] According to an embodiment of the present disclosure, the second set determination submodule includes: a first sequence determination submodule, a third set determination submodule, and a fourth set determination submodule.

[0157] The first order determination submodule is used to determine a second execution order between the loop code blocks according to the execution logic between the loop code blocks.

[0158] The third set determination submodule is configured to determine, in accordance with the second execution order, memory access codes following the memory shielding instruction as a second set of codes to be verified in response to determining that the first executed loop code block contains memory shielding code.

[0159] The fourth set determination submodule is configured to determine, in accordance with the second execution order, the memory access code in the first executed loop code block as the second code set to be verified in response to determining that the first executed loop code block does not contain the memory shielding code.

[0160] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0161] According to an embodiment of the present disclosure, an electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method described above.

[0162] According to an embodiment of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute the method described above.

[0163] According to an embodiment of the present disclosure, a computer program product includes a computer program, and when the computer program is executed by a processor, the computer program implements the method described above.

[0164] Figure 8 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0165] like Figure 8As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. Computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to bus 804.

[0166] Various components in device 800 are connected to I / O interface 805, including an input unit 806, such as a keyboard, mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0167] The computing unit 801 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the code optimization method. For example, in some embodiments, the code optimization method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed onto the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the code optimization method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the code optimization method by any other suitable means (e.g., via firmware).

[0168] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-a-chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0169] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0170] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0171] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0172] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0173] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0174] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.

[0175] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A code optimization method, comprising: inserting a memory barrier code between at least two first memory access codes in each of a plurality of loop code blocks to be optimized in the code fragment to be optimized, to obtain a plurality of optimized loop code blocks; wherein at least two of the first memory access codes are respectively located in at least two target code sequences within the loop code block to be optimized, and at least two of the first memory access codes have a dependency relationship with each other; and The memory barrier code is inserted between at least two second memory access codes to obtain an optimized code fragment for the code fragment to be optimized; wherein the second memory access codes are respectively located in at least two loop code blocks within the code fragment to be optimized; the at least two loop code blocks include: the optimized loop code block; and at least two of the second memory access codes have a dependency relationship with each other.

2. The method according to claim 1, further comprising: The memory barrier code is inserted between at least two third memory access codes of each of a plurality of continuously executed initial code sequences of an initial loop code block to obtain a plurality of target code sequences of the loop code block to be optimized, wherein the third memory access codes are located in the continuously executed initial code sequences, and at least two of the third memory access codes have a dependency relationship with each other.

3. The method according to claim 2, wherein: Inserting the memory barrier code between at least two third memory access codes of each of the multiple continuously executed initial code sequences of the initial loop code block to obtain the multiple target code sequences of the loop code block to be optimized includes: determining a target location for the memory barrier code in the initial code sequence; Generate an intermediate code sequence by inserting the memory barrier code at the target location; In response to determining that at least two fourth memory access codes in the intermediate code sequence have a dependency relationship, generating the target code sequence by inserting the memory barrier code between the at least two fourth memory access codes; and In response to determining that there is no dependency relationship between any at least two fourth memory access codes in the intermediate code sequence, the intermediate code sequence is determined to be the target code sequence.

4. The method according to claim 3, wherein: The initial code sequence further includes a plurality of code groups located between at least two third memory access codes, the plurality of code groups including non-memory access codes; Determining a target location for the memory barrier code in the initial code sequence includes: determining first positions of the at least two third memory access codes in the initial code sequence; A position adjacent to the first position along a first predetermined direction is determined as the target position.

5. The method according to claim 3, wherein: The initial code sequence further includes a plurality of code groups located between at least two third memory access codes, the plurality of code groups including non-memory access codes and at least one fifth memory access code; Determining a target location for the memory barrier code in the initial code sequence includes: Obtaining a first execution duration required for each target memory access code in the initial code sequence to be executed and a second execution duration required for each non-memory access code to be executed; the target memory access code includes the third memory access code and the at least one fifth memory access code; Obtaining a plurality of estimated waiting times for a plurality of candidate positions according to the first execution time and the second execution time; and The target location is determined from the multiple candidate locations based on the multiple expected waiting times.

6. The method according to claim 5, wherein: The plurality of candidate positions include a first candidate position adjacent to the third memory access code along a first predetermined direction and a second candidate position adjacent to the target memory access code along the first predetermined direction; The obtaining, according to the first execution time and the second execution time, a plurality of estimated waiting times for a plurality of candidate positions, respectively, includes: calculating, based on the first execution time and the second execution time, respective estimated waiting times of a plurality of target memory access codes located before the plurality of candidate positions; In the initial code sequence, determining a maximum value among the respective expected waiting times of a plurality of target memory access codes located before the first candidate position as a first expected waiting time for the first candidate position; In the initial code sequence, determining a maximum value among the respective expected waiting times of a plurality of target memory access codes located before the second candidate position as a second expected waiting time for the second candidate position; In response to determining that the first estimated waiting time is less than or equal to the second estimated waiting time, determining the first candidate location as the target location; and In response to determining that the first expected waiting time is greater than the second expected waiting time, the second candidate position is determined to be the target position.

7. The method according to claim 6, wherein the calculating, based on the first execution time and the second execution time, respectively the estimated waiting time of a plurality of target memory access codes located before a plurality of candidate positions comprises: For each target memory access code, determining the sum of the durations required for executing a plurality of code groups following the target memory access code in the initial code sequence as the idle duration of each target memory access code; as well as According to the execution time required for each target memory access code to be executed and the idle time of each target memory access code, the estimated waiting time of each target memory access code is obtained.

8. The method according to any one of claims 1 to 7, wherein The step of inserting a memory barrier code between at least two first memory access codes of each of a plurality of loop code blocks to be optimized in the code fragment to be optimized to obtain a plurality of optimized loop code blocks includes: generating a first set of codes to be verified for each target code sequence according to the execution logic between the plurality of target code sequences in the loop code block to be optimized and the position of the memory shielding code in each target code sequence; and In response to determining that a candidate memory access code in the first to-be-verified code set has a dependency relationship with a candidate memory access code in a first target code sequence among the multiple target codes, the candidate memory access code is used as the first memory access code, and the memory barrier code is inserted into the first target code sequence.

9. The method according to claim 8, wherein Generating a first set of codes to be verified for each target code sequence according to the execution logic between each target code sequence in the loop code block to be optimized and the position of the memory shielding instruction in each target code sequence includes: determining a first execution order between the target code sequences according to the execution logic between the target code sequences in the loop code block to be optimized; In response to determining that a previously executed target code sequence includes a memory shielding code in the first execution order, determining memory access codes following the memory shielding code as the first set of codes to be verified; and According to the first execution order, in response to determining that a previously executed target code sequence does not have a memory shielding instruction, the memory access code in the previously executed target code sequence is determined as the first set of codes to be verified.

10. The method according to any one of claims 1 to 9, wherein Inserting the memory barrier code between at least two second memory access codes to obtain an optimized code fragment for the code fragment to be optimized includes: generating a second set of codes to be verified for each of the target code sequences according to the execution logic between the multiple optimized loop code blocks in the code fragment to be optimized and the position of the memory barrier code in each loop code block; and In response to determining that a dependency relationship exists between a candidate memory access code in a second to-be-verified code set and a candidate memory access code in a second target code sequence among the plurality of target code sequences, the memory barrier code is inserted into the second target code sequence.

11. The method according to claim 10, wherein: Generating a second set of codes to be verified for each target code sequence according to the execution logic between each loop code block in the code fragment to be optimized and the position of the memory barrier code in each loop code block includes: Determining a second execution order between the loop code blocks according to the execution logic between the loop code blocks; In response to determining that a previously executed loop code block contains memory shielding code according to the second execution order, determining memory access code following the memory shielding instruction as the second set of codes to be verified; and According to the second execution order, in response to determining that the previously executed loop code block does not contain memory shielding code, the memory access code in the previously executed loop code block is determined as the second set of codes to be verified.

12. A code optimization device comprising: a first optimization module, configured to insert a memory barrier code between at least two first memory access codes in each of a plurality of loop code blocks to be optimized in a code segment to be optimized, to obtain a plurality of optimized loop code blocks; wherein at least two of the first memory access codes are respectively located in at least two target code sequences within the loop code block to be optimized, and at least two of the first memory access codes are dependent on each other; and A second optimization module is configured to insert the memory barrier code between at least two second memory access codes to obtain an optimized code fragment for the code fragment to be optimized; wherein the second memory access codes are respectively located in at least two loop code blocks within the code fragment to be optimized; the at least two loop code blocks include: the optimized loop code block; and at least two of the second memory access codes have a dependency relationship with each other.

13. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 11.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-11.

15. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 11.

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