12 results about "Shared variables" patented technology

The application discloses a file cleaning method and device, the method is executed by a file cleaning server, and the method comprises the following steps: setting a shared variable which can be accessed by a first component and a second component, the first component and the second component are asynchronous components; enabling the first component to detect a cleaning state of the current time, and determining the value of the shared variable according to the detected cleaning state of the current time; enabling the second component to read the value of the shared variable, and determining whether to clean the files to be cleaned according to a preset file cleaning strategy according to the read value of the shared variable. By introducing the shared variable of the cleaning state of the current time, the application can dynamically identify the time of the executable cleaning operation, effectively utilize the system idle time for file cleaning, and reduce the influence of cleaning a large number of files on actual business during the business peak period. In addition, the second component of the application detects the cleaning state of the current time through an asynchronous thread, and does not affect the execution efficiency of the main process.

The invention relates to a register resource allocation method, computer equipment, a readable storage medium and a program product. The method comprises the following steps: constructing a function group through a calling relationship between functions, wherein the function group comprises a coroutine kernel function and at least one coroutine subfunction; creating a resource record table corresponding to the function group, wherein the resource record table is used for recording register resources allocated to coroutine kernel functions and / or coroutine sub-functions in the function group; and carrying out register allocation on the coroutine kernel function and the coroutine sub-function in the function group based on the resource record table. By adopting the method, the requirements of local variable register resource isolation and shared variable register resource consistency in a collaborative mode can be met, so that the parallel computing efficiency is improved.

A PLC device according to the present disclosure comprises: a reference determination part that determines the presence or absence of reference by a plurality of program modules to shared variables and / or common data types in scope units; and a reference state output part that outputs, on the basis of the determination of the presence or absence of the reference, a list of the shared variables and / or common data types in scope units that is referred to by each of the program modules.

The disclosure relates to a method for generating an output source code (POSC) that can be executed in parallel over a processor with at least two cores. This method is implemented by an electronic device with a processor and memory, and involves the following steps: Obtaining a syntax tree data structure (STDS) of an input source code (ISC) written in a non-concurrent programming language, with precompiling directives (PCD), into the memory of the electronic device. Identifying at least one shared variable within the input source code (ISC) using the syntax tree data structure (STDS). Determining the location of the at least one mutex (MTX) in the syntax tree data structure (STDS) for the output source code (POSC) as a function of the precompiling directives (PCD) of the input source code. Determining task ordering in the syntax tree data structure (STDS) for the output source code (POSC), as a function of the precompiling directives (PCD) of the input source code. Generating the output source code (POSC) from the syntax tree data structure (STDS).

The present disclosure relates to reusable barriers for synchronization between multiple processes. In one aspect, a system and method for facilitating synchronization between processes is provided. During operation, the system can execute multiple processes in parallel on one or more computing nodes. In response to a first process calling a barrier function, the system can suspend execution of the first process, and in response to determining that the first process has gained access to a variable shared by at least a subset of the multiple processes, the system can update the shared variable. The system can release the shared variable to a second process in the subset to update the shared variable when the second process calls the barrier function, and determine whether all processes in the subset have updated the shared variable. In response to the shared variable having been updated by all processes in the subset, the system can resume execution of all processes in the subset.

The application discloses a kind of on-orbit software load balancing methods of multi-core CPU, comprising the following steps: S1, thread pool is formed by the functional item abstraction of on-orbit software;S2, multi-core CPU is provided with at least 4 cores, wherein the algorithm thread, I / O thread is respectively limited in two CPU cores, the rest thread is set soft affinity, and according to the busy state of the rest CPU core, it is selected to run in corresponding CPU core;S3, algorithm thread, I / O thread, remote telemetry thread carry out data interaction by shared variable, and the competition problem between threads is solved by protecting shared variable by mutual exclusion, condition variable;S4, when on-orbit software needs to be programmed on-orbit, main thread stops corresponding thread, replaces old shared library with upgraded shared library, and restarts thread operation;Or terminate corresponding thread, add new shared library to specified position, recreate the thread, and open and load new shared library in thread operation.

A multi-domain masked AND gate includes inner-domain calculations, re-sharing, register stage, cross-domain calculations, and compression. The inner-domain multiplication and the re-sharing are calculated prior to storing the re-shared variables in the register stage. Thus, the inputs to the cross-domain multiplication and the compression are performed on variables that have been refreshed by additional randomness. This AND gate does not need statistically independent inputs, is secure in the probing model even in the presence of glitches, also known as the robust probing model. A two-domain input and two domain output AND gate can be implemented using six (6) registers, four (4) two input logical AND gates, and eight (8) exclusive-OR (XOR) gates. The AND gate may also be used to implement an AES S-box that has two (2) register stages and takes two (2) clock cycles per computation.

The application relates to a register resource allocation method, computer equipment, a readable storage medium and a program product. The method comprises the following steps: constructing a function group through a calling relationship between functions, the function group comprising a coroutine kernel function and at least one coroutine sub-function; creating a resource record table corresponding to the function group, the resource record table being used for recording register resources allocated for the coroutine kernel function and / or the coroutine sub-function in the function group; and performing register allocation for the coroutine kernel function and the coroutine sub-function in the function group based on the resource record table. The method can meet the demand that local variable register resources are isolated and shared variable register resources are consistent in a cooperative mode, thereby improving parallel computing efficiency.

The purpose of the present invention is to reduce the burden on a user for creating a control program when a call process for accessing a shared variable is not definitely used during creation of the control program. The control system includes: a plurality of peripheral devices; and a control device that includes a shared variable that can be shared with a plurality of peripheral devices, the control device including: a library generation unit that extracts shared variable information including at least information about an offset and a size from the definition of the shared variable, and generates a shared variable access library for accessing the shared variable on the basis of the shared variable information; each of the plurality of peripheral devices includes: an analysis unit that analyzes a reference code referring to a shared variable from an executed control program; a conversion unit that inserts, at the position of the reference code analyzed by the analysis unit, a call conversion control program of the shared variable access library that accesses the shared variable referenced by the reference code; and an execution unit that executes the control program converted by the conversion unit.

The application discloses a shared variable dependency chain break detection method and device, relates to the technical field of multiprocessor programming, and comprises the following steps: coupling two detection channels of a static reverse assembly channel and a dynamic PMU channel, wherein the static reverse assembly channel utilizes the principle that the relevant reverse assembly code will change when the shared variable dependency chain breaks, the dynamic PMU channel utilizes the principle that the number of relevant PMU events in the program running process will change when the shared variable dependency chain breaks, a shared variable dependency chain break detection architecture is constructed, and the technical problems that the performance overhead of a dynamic analysis method is large, and the automation degree of a static analysis method is limited in the related art are solved. In addition, the coverage scene of a formal verification method is limited, and it is difficult to reproduce the complex competition conditions of a production environment, technical effects that the accuracy and efficiency of detection are effectively improved, the dynamic detection overhead is reduced, and the competition conditions in a real production environment can be covered are achieved.

One aspect provides a system and method for facilitating synchronization among processes. During operation, the system may execute, in parallel on one or more compute nodes, a plurality of processes. In response to a first process calling a barrier function, the system may pause execution of the first process, and in response to determining that the first process gains access to a variable shared by at least a subset of the plurality of processes, the system may update the shared variable. The system may release the shared variable to a second process in the subset to update the shared variable when the second process calls the barrier function and determine whether all processes in the subset have updated the shared variable. In response to the shared variable having been updated by all processes in the subset, the system may resume the execution of all processes in the subset.

The application relates to the technical field of artificial intelligence chips, and provides a register access instruction generation method, a register access method, a host, equipment, a server and a medium, which comprise the following steps: extracting cross-thread bundle shared variables in kernel code; based on the total private register demand of the kernel code, dividing physical register resources of a hardware device into a private register pool and a shared register pool; determining a shared base address of the shared register pool, and allocating a static offset to each cross-thread bundle shared variable; and converting access statements in the kernel code for each cross-thread bundle shared variable into target access instructions according to the shared base address and the static offset. The application divides the shared register pool, and generates target access instructions by using a unified shared base address combined with a static offset, so that high-speed register-level data sharing and low-delay communication of cross-thread bundles are realized, cross-thread bundle synchronization and memory access delay are reduced, and the utilization rate of on-chip physical register resources is improved.