44 results about "Multiplication operator" patented technology

A method for antenna subset selection by joint processing in RF and baseband in a multi-antenna systems. L_t input data streams are generated in a transmitter for either diversity transmission or multiplexing transmission. These streams are modulated to RF signals. These signals are switched to the t branches associated with the t transmit antennas, and a phase-shift transformation is applied to the RF signals by a t×t matrix multiplication operator Φ₁, whose output are t≧L_t RF signals. These signals are transmitted over a channel by t antennas. The transmitted signals are received by r antennas in a receiver. A phase-shift transformation is applied to the r RF signals by a r×r matrix multiplication operator Φ₂. L_r branches of these phase shifted streams are demodulated and further processed in baseband to recover the input data streams.

A block matrix multiplication vectorization method supporting a vector processor with multiple MAC (multiply accumulate) operational units includes the steps of (1), determining the optimum block size of submatrix, the quantity of lines and rows of the submatrix of a multiplier matrix B and the quantity of lines and rows of the submatrix of a multiplier matrix A according to the quantity p of vector processing elements (VPE) of the vector processor, the quantity m of the MAC operational units in the VPE, the capacity s of a vector memory and data size d of matrix elements, (2) equally dividing the capacity s of the vector memory into two storage areas of Buffer 0 and Buffer 1, and realizing multiplication of the submatrix in the Buffer 0 and the Buffer 1 in a Pingpong mode until completing the multiplication operation of the whole matrix. The block matrix multiplication vectorization method has the advantages of easiness in implementing, convenience in operation, capabilities of improving parallelism of the vector processor and increasing operation efficiency thereof, and the like.

The invention discloses an optimized Montgomery modular multiplication method, an optimized modular square method and optimized modular multiplication hardware. The optimization is carried out based on an original FIOS (Finely integrated operand scanning) algorithm. The optimized modular multiplication hardware mainly comprises three single-port SRAMs, a double-port SRAM, a 32-bit multiplier, a 34-bit adder, a 4-2 compressor, a 64-bit register and six 32-bit registers. According to the optimized Montgomery modular multiplication method, the optimized modular square method and the optimized modular multiplication hardware, a high-radix modular multiplier of a two-stage parallel assembly line is adopted, the AB operation is completed through a first-stage 32-bit multiplier, the T+AB+C operation is completed through a second-stage adder, the 32-2048-bit modular multiplication operation is achieved, the area of a chip is reduced, and the modular multiplication operation performance is improved.

The invention discloses a matrix operation-based parallel computing method, which is mainly designed for simplifying a parallel acceleration program and reducing the realizing difficulty of a parallel algorithm. The method comprises the following steps of: describing an algorithm to be described as a matrix operation formula; abstracting a computing task as an abstracted multiplication operator and/or an abstracted addition operator among all matrixes with certain element types; mapping the matrix operation into an accelerator programming model; and executing the operation and outputting a result by using an accelerator. The method describes the parallelism of the algorithm by using a matrix operation rule so as to reduce the difficulty in describing the parallel algorithm. Meanwhile, the parallel algorithm is realized on the base of the generalized matrix operation, the characteristics of a specific algorithm can be eliminated as many as possible, the mapping of more general parallel algorithm to the accelerator is realized, and scheduling software can be designed according to the common matrix operation, so that the software can be more generally suitable for various algorithms, repetitive work for developing accelerator scheduling codes is reduced and a development process is simplified.

The invention discloses a multiplication device and a multiplication method. A multiplier input module is called to input a multiplier with wide positioning to a multiplier. A high and low bits of thepositioning wide multiplier are split by calling the high and low bits splitting module. A complement module is called to complement the bit value after splitting; a multiplication module is called to perform multiplication operation on the bit value after complementing according to the given multiplication mode, and the operation result corresponding to the multiplication mode is obtained. A time-sharing transport module selects results obtained through multiplication according to a first multiplication mode, a second multiplication mode and a third multiplication mode in a time-share manneraccording to a given sequence and sends to an adder. A result accumulating module is called to accumulate the multiplication result sent to the adder to obtain the multiplier operation value. The invention realizes the support of the low bit width multiplier to the high bit width operation through the time expansion, solves the problem of completing the multiplication operation of the large bit width multiplier through the multiplier with less bit width, and reduces the complexity of the multiplication operation.

The invention relates to an SM2 elliptic curve signature verification hardware system and method for resisting differential power consumption attack, the anti-differential power consumption attack method of the invention is applied to scalar multiplication, by adding the improved randomized scalar method to the point multiplication operation, the correlation between the real key information and the power curve is destroyed, which makes it difficult for the power analysis to obtain the information to resist the power analysis, and ensures the security of the differential power attack, thus playing a very good role in resisting the differential power attack. And this method is simple and easy to implement, and can be integrated into a variety of encryption chips and other hardware devices.

The present invention relates to the field of information security and microprocessor design, in order to realize the conversion of modular multiplication into simple decimal addition and multiplication through FIOS modular multiplication algorithm, fully reduce the area of ​​modular multiplication operation unit, and effectively avoid writing back a large amount of intermediate data process. From the perspective of hardware implementation, it improves the computational efficiency of the algorithm and further saves computational resources, fundamentally reduces the time and space overhead of encryption and decryption, and effectively improves the encryption and decryption performance of RSA. The technical solution adopted by the present invention is that, before encryption, a dual-core parallel RSA encryption processing method needs to rely on a certificate authority (CA) as a trusted third party to be responsible for the generation, storage, maintenance, and revocation of the user's private key and public key certificate Link, when encrypting, user B executes the operation c=m ^e (modN) and send the encrypted information c to user A; when decrypting, user A uses his own private key d to perform operations on the ciphertext c to recover the plaintext. The invention is mainly applied to information security processing.

Multistage Wiener filters (MWF) represent a component of the MWF as an un-normalized vector of filter coefficients within a finite impulse response (FIR) filter in a manner that avoids reliance on the 2-norm operation of the un-normalized vector of coefficients. The 2-norm operation can be replaced by less expensive operations performed elsewhere in the MWF. Preferably the filter adds only a few additional addition, subtraction and multiplication operations to compensate for the elimination of the square root and the division operations used for the 2-norm operation. As a result, it is possible to eliminate all or nearly all of the square rod and arithmetic division operations of at least some implementations of the MWF.

The invention relates to an all-in-one irreducible polynomial based finite field multiplier which comprises a controller, an input control module, an output control module, a finite field multiplier and an operation module, wherein the controller is used for controlling and scheduling data transmission among the input control module, the output control module and the finite field multiplier; the input control module is used for inputting a multiplication operation number a(x) and a multiplication operation number b(x) when detecting that a finite field GF(2n) has an all-in-one irreducible polynomial; the finite field multiplier is used for calling the operation module to carry out finite field multiplication operation on the multiplication operation number a(x) and the multiplication operation number b(x) to obtain a multiplication operation result c(x); the operation module is used for implementing and logical operation, exclusive or logic operation and modular operation; the output control module is used for outing the multiplication operation result c(x). By adopting the multiplier, the operation efficiency of finite field multiplication is improved.

The invention provides a multiplier based on a memristor RRAM. The multiplier of the voter logic is given based on the original adder, the structure of the Wallace tree is adopted for operation, the multiplication operation is converted into the corresponding addition operation, and by utilizing the Wallace tree structure, a plurality of n-Bit numbers are added up to 2n-Bit numbers, and each fulladdition operation can be performed simultaneously by using voter logic. The multiplier of the invention improves the overall running speed and reduces the area of the device.

The invention discloses a fast iteration adaptive filtering method. The method is implemented by adopting the steps of 1, performing data collection on dual-channel digital signals; 2, performing filtering and noise reduction processing on the collected data by adopting improved LMS (Least Mean Square) adaptive iteration filtering; and 3, adjusting a step length factor until optimal target digitalsignals are obtained. The fast iteration adaptive filtering method eliminates an operation of using a residual scalar e(n) in a weight factor iteration formula to serve as a multiplication factor, and controls the adjustment direction by a symbol of the residual scalar e(n), thereby enabling the convergence speed to be greatly improved, and simplifying the computational complexity. The fast iteration adaptive filtering method is applicable to any LMS operating environment and algorithm, and particularly applicable to operating in real time on various 16-bit MCUs.

The invention discloses a feature extraction method and system applied to deep learning. An existing deep learning calculation mode is improved; in the prior art, for feature extraction in the deep learning, a group of digital signals to be subjected to feature extraction and digital signals of a filter need to be subjected to convolution; the two types of the digital signals are converted into optical signals; at the moment, the optical signals can be simply converted into a frequency domain; the convolution on a time domain is equivalent to the point multiplication on the corresponding frequency domain; the convolution on the time domain is very complex; and the point multiplication operation on the frequency domain can be much simpler. The calculation amount in the deep learning can beeffectively reduced; and after part of the operation is converted into optical calculation, the calculation speed of the part is changed to the optical calculation speed, so that the calculation timeis greatly shortened.

The invention relates to the information security technical field, in particular to a modular multiplication method and an extensible modular multiplier, namely an extensible method used for calculating classic modular multiplication A B mod M and a corresponding extensible modular multiplier based on the Jeong - Burleson algorithm. According to the modular multiplication method and the extensible modular multiplier, due to the fact that tasks are distributed to each processing unit and operated word by word in each processing unit, on one hand, modular multiplication operation in any length or with length alterable can be calculated by utilizing limited logical resources and enough memorizers, and calculated amount is small in the situation that multiplicators or multiplicands change constantly; on the other hand, an approach for selecting design parameters and optimizing performance is provided; and meanwhile, a novel precomputation value and a low latency structure enable operation efficiency to be improved.

The invention discloses a digital image encryption method, decryption method and system based on a chaotic system, and belongs to the field of chaotic image encryption, and the encryption method comprises the steps: taking a one-dimensional chaotic mapping as a seed mapping, introducing a multiplication operator and a modular operator, constructing a strong dynamic chaotic mapping, initializing a control parameter of strong dynamic chaotic mapping by using the hash value of the digital image to be encrypted and the encryption key; iterating the strong dynamic chaotic mapping for multiple times, extracting bits with a preset length from a chaotic state value obtained by each iteration to form a corresponding pseudo-random sequence, and diffusing image pixels of the digital image to be encrypted by using the pseudo-random sequence; and performing multiple iterations on the strong dynamic chaotic mapping again, converting a chaotic state value obtained by each iteration into an integer value in a set interval until a set number of different integer values are obtained, and performing scrambling operation on image pixels after diffusion processing to obtain a final encrypted image. And the digital image is encrypted safely and effectively.

Techniques are disclosed relating to circuitry configured to perform reciprocal-based floating-point division. In some embodiments, floating-point circuitry includes reciprocal circuitry configured to generate a reciprocal of a divisor, multiplication circuitry configured to multiply the reciprocal results with a dividend, and circuitry configured to clear a least significant bit of an integer representation of the multiplication output to generate a modified multiplication output. The floating-point circuitry may be configured to convert the modified multiplication output to a representation using the first precision to generate a division output. In some embodiments, the refinement using the integer representation may provide correctly-rounded subnormal division results. The disclosed techniques may improve accuracy, reduce processing time, and/or reduce instructions needed for floating-point division, with little to no increase in chip area.

A method in an elliptic curve cryptographic system, the method being executed by an electronic device and including a multiplication operation of multiplying a point of an elliptic curve by a scalar number, the point having affine coordinates belonging to a Galois field, the multiplication operation including steps of detecting the appearance of a point at infinity during intermediate calculations of the multiplication operation, and of activating an error signal if the point at infinity is detected and if the number of bits of the scalar number processed by the multiplication operation is lower than the rank of the most significant bit of an order of a base point of the cryptographic system.

A circuit for calculating the fused sum of an addend and product of two multiplication operands, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplication operands are in a lower precision format than the addend, with q>2p, where p and q are the mantissa size of the multiplication operand and addend precision formats. The circuit includes a p-bit multiplier receiving the mantissas of the multiplication operands; a shift circuit aligning the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplication operands; and an adder processing q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa.