Method for defining parallel dual butterfly computation fast Fourier transform processor structure
A Fourier transform and parallel processing technology, applied in the information field, can solve problems such as high clock frequency, increased addressing complexity, and complex multiplier consumption and occupation, so as to improve computing speed, solve computing speed and hardware consumption volume effect
Inactive Publication Date: 2006-06-14
SHANGHAI JIAOTONG UNIV
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Problems solved by technology
The traditional single-memory structure and dual-memory structure occupy less hardware resources, but the throughput is low and requires a higher clock frequency
In order to effectively improve the calculation speed of FFT, it was found through literature search that Byung S.Son et al. published an article "High-speed FFT Processor forOFDM Systems" (high-speed FFT processor in OFDM systems, IEEE International Conference on Circuits and Systems), this paper proposes a single-memory grouping scheme based on the traditional single-memory structure, which greatly improves the operation speed of the FFT processor and occupies Smaller memory, but increased addressing complexity and complex multiplier consumption, thus occupying more hardware resources
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[0026] Such as figure 1 Shown, provide following embodiment in conjunction with content of the present invention:
[0027] The method of the present invention is used for the design of 64 FFT processors in the wireless local area network standard IEEE 802.11a, and with the time parameter (t in IEEE 802.11a FFT =3.2μs) as standard.
[0028] The first step is to perform parallel butterfly calculation processing. The 64-point radix-four frequency extraction FFT processor is divided into 3 stages, each stage processes 64 data, and each butterfly operation processes 3 clocks to read 4 data, and the number of clocks consumed by each stage is n one_stge =64 / 4×3+12=60 clocks, the total number of clocks consumed by a 64-point FFT process is n FFT =n one_stage ×3=60×3=180 clocks. If a 60MHz system clock is used, it takes 180 / 60MHz=3μs<3.2μs for a 64-point FFT processor to complete a process. By adopting parallel butterfly calculation processing, the obtained FFT processor has been...
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The invention relates to a method for determining the structure of a parallel double-butterfly fast Fourier transform processor, which belongs to the field of information technology. The present invention improves the core unit in the fast Fourier transform processor - the butterfly calculation unit, and obtains a parallel double butterfly calculation processing method. The processor and the adder are processed in parallel to obtain a parallel butterfly calculation structure, and then perform double butterfly calculation processing, that is, the input of the butterfly calculation unit is grouped according to the corresponding rotation factor, and then the input data is divided according to whether the butterfly calculation process contains multiplication The processor is divided into two butterfly calculation processing units for processing, and a parallel double butterfly calculation fast Fourier transform processor structure is obtained. The present invention effectively improves the operation speed of the fast Fourier transform processor, occupies less hardware resources, especially multiplier resources, thereby better solving the problem between the operation speed and hardware consumption in the fast Fourier transform processor. contradiction.
Description
technical field [0001] The invention relates to a method for determining the structure of a fast Fourier transform processor, in particular to a method for determining the structure of a parallel double-butterfly fast Fourier transform processor, which belongs to the field of information technology. Background technique [0002] Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier technology, which divides a wideband channel into several orthogonal narrowband sub-channels, and transmits information on each sub-channel simultaneously, thereby improving the channel utilization rate. Moreover, inter-symbol interference is reduced by adding a cyclic prefix, which enhances the ability of the system to resist multipath interference. In recent years, OFDM technology has been more and more widely used because of its excellent performance. Not only has it been successfully applied in digital TV and digital audio broadcasting, but also wireless local area network sta...
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IPC IPC(8): H04J11/00H04L27/32
Inventor 田继锋姜海宁宋文涛罗汉文张海滨
Owner SHANGHAI JIAOTONG UNIV
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