Block matrix multiplication vectorization method supporting vector processor with multiple MAC (multiply accumulate) operational units

Abstract

A block matrix multiplication vectorization method supporting a vector processor with multiple MAC (multiply accumulate) operational units includes the steps of (1), determining the optimum block size of submatrix, the quantity of lines and rows of the submatrix of a multiplier matrix B and the quantity of lines and rows of the submatrix of a multiplier matrix A according to the quantity p of vector processing elements (VPE) of the vector processor, the quantity m of the MAC operational units in the VPE, the capacity s of a vector memory and data size d of matrix elements, (2) equally dividing the capacity s of the vector memory into two storage areas of Buffer 0 and Buffer 1, and realizing multiplication of the submatrix in the Buffer 0 and the Buffer 1 in a Pingpong mode until completing the multiplication operation of the whole matrix. The block matrix multiplication vectorization method has the advantages of easiness in implementing, convenience in operation, capabilities of improving parallelism of the vector processor and increasing operation efficiency thereof, and the like.

Description

technical field [0001] The invention mainly relates to the technical field of data processing, in particular to a block matrix multiplication vectorization method supporting a multi-MAC operation unit vector processor. Background technique [0002] With the increasing demand for high-performance computing for computing-intensive applications such as solving large-scale dense linear equations, 4G wireless communications, radar signal processing, high-definition video and digital image processing, computer architectures have undergone significant changes, and many new architectures have emerged, such as Many-core architecture, heterogeneous multi-core architecture, stream processor architecture and vector processor architecture, etc. These new architectures integrate multiple processor cores on a single chip, and each core contains a wealth of computing components , greatly improving the computing performance of the chip; at the same time, it also poses new challenges to softw...

AI Technical Summary

Problems solved by technology

The vector data access unit supports Load / Store of vector data and provides a large-capacity dedicated vector memory instead of the Cache mechanism of a single-core processor. The existing block matrix multiplication method is not suitable for this type of vector processor

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