Fusion processing device and method for floating-point number multiplication-addition device

Abstract

The invention provides a fusion processing device and a fusion processing method for a floating-point number multiplication-addition device. The method comprises the following steps of: inputting real parts and imaginary parts of a multiplier and a multiplicand of a floating point complex number into floating-point multiplication modules M0 and M1, and performing floating-point multiplication operation, wherein output results present products by using a carry bit and a partial sum; inputting the products into a floating-point addition module A2, and performing floating-point addition operation, wherein the output results present addition operation by using the carry bit and the partial sum; inputting the output results which present the addition operation into floating-point addition modules A0 and A1 simultaneously; inputting addends input from the outside into the floating-point addition modules A0 and A1, and performing floating-point addition operation; and outputting operation results. The device and the method can be better applied to butterfly computation of Fourier transform; and by the device and the method, operation steps can be simplified, hardware resources are easy to save, and the multiplication-addition operation of the floating point complex number is realized by less resources.

Description

technical field [0001] The present invention relates to the field of a central processing unit (Central Processing Unit (CPU)) of a computer or a digital signal processor, in particular to a floating-point complex multiplier-adder fusion processing device and method. Background technique [0002] After the invention of the computer, researchers have carried out a lot of research work around the design of the basic unit of calculation, especially the multiplication and addition of floating-point numbers in the form of complex numbers, and the design of multiplication and addition cascades. [0003] So far, many patents have been applied for in the design of floating-point multiplication and addition, for example, the patent "a kind of floating-point complex multiplier" (Chen Zezong, He Liang, Ke Hengyu, Wuhan University). However, this method only analyzes the method of multiplication, and does not further analyze how to simplify the interface from multiplication output to ad...

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However, this method only analyzes the method of multiplication, and does not further analyze how to simplify the interface from multiplication output to addition input

Another patent has been applied for "Apparatus and Method for Optimizing the Execution of x87 Floating-Point Addition Instructions by Microprocessors" (Tom Elmore, Terry Parkes, VIA Electronics, Inc.), which focuses more on explaining instructions The impact on the execution efficiency of floating-point numbers has not been refined to how the hardware is implemented

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