Matrix multiplication acceleration method for supporting variable blocks

A matrix multiplication and matrix technology, applied in the field of matrix multiplication acceleration that supports variable block, can solve the problems of no block optimization and the reduction of accelerator computing efficiency.

Active Publication Date: 2015-09-09
NAT UNIV OF DEFENSE TECH
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AI Technical Summary

Problems solved by technology

When the block size does not match the matrix accelerator chain length, the accelerator computing efficiency will drop significantly
As far as we know, there is no published literature related to the design of matrix multipliers that support variable partitioning, and there is no related research on the block optimi

Method used

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  • Matrix multiplication acceleration method for supporting variable blocks
  • Matrix multiplication acceleration method for supporting variable blocks
  • Matrix multiplication acceleration method for supporting variable blocks

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Embodiment Construction

[0048] Such as figure 1 As shown, the steps of this embodiment supporting variable block matrix multiplication acceleration method include:

[0049] 1) Input matrix A of M*N and matrix B of N*R required for matrix multiplication;

[0050] 2) Determine the sub-block size S according to the scale of matrix A and matrix B i , the matrix A is scaled as S i *N sub-blocks are divided into rows, and the matrix B is N*S in size i The sub-blocks are divided into blocks by columns, so that the matrix multiplication operation is equivalent to the multiplication operation of multiple sub-blocks;

[0051] 3) Generate a DMA descriptor for the data required for each sub-block multiplication operation, construct a DMA descriptor linked list for all sub-block multiplication operations and store them in the main memory;

[0052] 4) For each sub-block multiplication operation, read the data required for the sub-block multiplication operation from the DMA descriptor linked list of the main me...

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Abstract

The invention discloses a matrix multiplication acceleration method for supporting variable blocks. The steps include: a matrix A and a matrix B are inputted, the size Si of a subblock is determined according to the scales of the matrix A and the matrix B, the matrix A is partitioned in lines regarding the subblock with the scale of Si*N as the unit, the matrix B is partitioned in rows regarding the subblock with the scale of N*Si as the unit, a DMA descriptor is generated for required data of multiplication operation of each subblock, all the DMA descriptors are constructed to a DMA descriptor list, for the multiplication operation of each subblock, the required data of the multiplication operation of the subblocks is read according to the DMA descriptor list in a main memory, the multiplication operation of the subblocks is conducted via a processing unit chain of a matrix multiplication accelerator, and the result is written back to the main memory via the DMA. The method is advantageous in that variable blocks can be supported, the number of employed processing units can be adjusted according to the size of the blocks, and the acceleration efficiency for accelerating the multiplication operation of non-uniform matrixes is high.

Description

technical field [0001] The invention relates to a matrix multiplication acceleration technology under an embedded platform, in particular to a matrix multiplication acceleration method supporting variable partitioning. Background technique [0002] With the development of semiconductor manufacturing technology and the advancement of integrated circuit technology, more and more transistors can be integrated on a single chip, and the use of programmable devices, especially FPGA (Field Programmable Gate Array) chips for design has become the current standard for building embedded systems. And an important way of hardware acceleration platform. The current FPGA chips provide dedicated arithmetic modules, a large number of logic resources and storage resources, as well as external memory interfaces, network interfaces and other peripheral interfaces, which provide conditions for building high-performance computing systems and make FPGA reconfigurable computing systems an accelera...

Claims

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Application Information

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IPC IPC(8): G06F17/16G06F7/523
Inventor 文梅沈俊忠乔寓然杨乾明苏华友肖涛陈照云张春元
Owner NAT UNIV OF DEFENSE TECH
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