Semiconductor device, manufacturing method and transistor circuit

A technology of transistors and semiconductors, which is applied in semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve the problems of thin insulating layers that are easily damaged, and the withstand voltage of GaN-HEMT is not high, so as to improve the withstand voltage Effect

Inactive Publication Date: 2012-09-19
TRANSPHORM JAPAN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The thin insulating layer is easily damaged if a high voltage is applied between the source and drain
In other words, the withstand voltage of GaN-HEMT itself is not high

Method used

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  • Semiconductor device, manufacturing method and transistor circuit
  • Semiconductor device, manufacturing method and transistor circuit
  • Semiconductor device, manufacturing method and transistor circuit

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment

[0037] (1) Structure

[0038] figure 1 is a circuit diagram of the transistor circuit 2 according to the present embodiment. The transistor circuit 2 comprises a first high electron mobility transistor 4 and a second high electron mobility transistor 6 with a negative threshold voltage. exist figure 1 The equivalent circuits of the first high-electron-mobility transistor 4 and the second high-electron-mobility transistor 6 are shown in boxes drawn with dotted lines in .

[0039] Such as figure 1 As shown, the second source S2 of the second high electron mobility transistor 6 is coupled to the first gate G1 of the first high electron mobility transistor 4 . Moreover, the second gate G2 of the second high electron mobility transistor 6 is coupled to the first source S1 of the first high electron mobility transistor 4 .

[0040] figure 2 is the cross section of the first high electron mobility transistor 4 . Such as figure 2 As shown, the first high electron mobility tr...

no. 2 Embodiment

[0119] Image 6 is a plan view of the transistor circuit 2b according to the present embodiment. In the first embodiment, a first high electron mobility transistor 4 is coupled to a second high electron mobility transistor 6 . On the other hand, if Image 6 As shown, in the transistor circuit 2 b according to this embodiment, a plurality of first high electron mobility transistors 4 are coupled to one second high electron mobility transistor 6 . Here, the first high electron mobility transistor 4 and the second high electron mobility transistor 6 are devices formed on the same substrate.

[0120] The structures of the first high electron mobility transistor 4 and the second high electron mobility transistor 6 are the same as those according to the first embodiment (refer to figure 2 , image 3 The structures of the first high electron mobility transistor and the second high electron mobility transistor described above are substantially the same. For example, a region bet...

no. 3 Embodiment

[0130] Figure 8 is a circuit diagram of the transistor circuit 2d according to the present embodiment. Such as Figure 8 As shown, the transistor circuit 2d is similar to the transistor circuit 2 of the first embodiment. Therefore, descriptions of parts common to the transistor circuit 2 of the first embodiment will be omitted.

[0131] Such as Figure 8 As shown, the transistor circuit 2d includes a first high electron mobility transistor 4a and a second high electron mobility transistor 6a.

[0132] (1) The first high electron mobility transistor

[0133] The first high electron mobility transistor 4 a includes a first gate G1 , a first field plate FP1 a and a second field plate FP2 .

[0134] Similar to the first field plate FP1 in the first embodiment, the first field plate FP1a is a field plate provided between the first gate G1 and the first drain D1. The first field plate FP1a may be a field plate of which a portion extends between the first gate G1 and the first...

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PUM

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Abstract

A transistor circuit includes a first high electron mobility transistor and a second high electron mobility transistor having a negative threshold voltage, wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor. The invention enables the withstand voltages of the high electron mobility transistors to be improved.

Description

technical field [0001] Embodiments discussed herein relate to a semiconductor device, a method for manufacturing the semiconductor device, and a transistor circuit. Background technique [0002] Due to the high breakdown electric field strength and high mobility of GaN, GaN-HEMTs (High Electron Mobility Transistors) are expected to be used as high-power switching devices. Here, a thin insulating layer is placed directly under the gate to drive the GaN-HEMT by a voltage of about several volts generated by an IC (Integrated Circuit). The thin insulating layer is easily damaged if a high voltage is applied between the source and drain. In other words, the withstand voltage of GaN-HEMT itself is not high. [0003] In order to solve the above problems, a semiconductor device having a field plate (FP) on a GaN-HEMT (hereinafter referred to as GaN-FP-HEMT) has been proposed. According to the GaN-FP-HEMT, the withstand voltage of the GaN-HEMT in relation to the source-drain volta...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/778H01L29/40
CPCH01L29/7787H01L29/41766H01L29/778H01L29/2003H01L23/291H01L29/402H01L29/404H01L29/41758H01L29/66462H01L23/3171H01L29/4236H01L2924/0002H01L2924/00
Inventor 竹前义博细田勉佐藤俊哉
Owner TRANSPHORM JAPAN
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