Non-volatile semiconductor memory

Abstract

A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has a first latch and a second latch that are selectively connected to the memory cell array and transfer data each other. A controller controls the reprogramming and retrieval circuits on data-reprogramming operation to and data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches in storing the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input / output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims benefit of priority under 35 USC §119 to Japanese Patent Applications Nos. 2000-63798 and 2000-323199 filed on Mar. 8, 2000 and Oct. 23, 2000, respectively, in Japan, the entire contents of which are incorporated by reference herein.BACKGROUND OF THE INVENTION[0002]The present invention relates to an electrically erasable programmable read-only memory (EEPROM). Particularly, this invention relates to a data-reprogramming / retrieval circuit that temporally stores data to be programmed or data to be retrieved for a caching function or a multilevel logical function.[0003]Focused on in the semiconductor industry is reduction of cost per bit for high-capacity flash EEPROMs used as a file memory by miniaturization of cell structure with process techniques and also by multilevel logic techniques for high capacity.[0004]FIG. 42 is a circuit block diagram of a data-reprogramming / retrieval circuit (called a page buffer herein...

AI Technical Summary

Benefits of technology

[0029]A purpose of the present invention is to provide a non-volatile semiconductor apparatus having a multilevel function for large storage capacity and a caching function for high-speed data load time.

[0042]The cooperation of the first and the second latches offers a high-speed EEPROM having a caching function.

[0046]The boosting capacitor controls the potential at the sense node while data on a bit line is being sensed, thus precisely adjusting two-level data “HIGH” and “LOW” retrieved at the sense node with respect to the threshold level of the sense amplifier for attaining wide margin of sensing.

[0048]These sequential sensing operations with potential boosting achieve accurate data judgement with no relation to variation in sense amplifier-threshold level by lowering data level “LOW” retrieved at the sense if it is not sufficiently low due to high turn-on resistance of a selected memory cell. Furthermore, lowering a retrieval voltage at the clamp transistor after data transfer prevents the potential at the sense node from going to a negative level, as a result of potential boosting, for retrieving originally sufficiently low level “LOW”.

Problems solved by technology

Increase in the number of cell array division, however, takes a long time to load data for each increase in data unit to be programmed.

Moreover, increase in the number of cell array division requires a large chip and causes high consumption of power.

Enhancement in effective programming speed only by cell array division takes a long data load time in two-level operation thus inefficient.

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