60results about How to "Reduce processor load" patented technology

Our invention is an apparatus and method to identify and simultaneously visualize and hear musical notes contained in an analog or digital sound wave. Musical notes are expanded into a language for the eye as well as the ear. An analog-to-digital converter processes an analog sound wave to provide a digital sound wave. Component frequencies of the digital sound waves are identified, filtered and translated to their corresponding musical note and volume. As the original digital sound wave is sent through a digital-to-analog converter and output to an audio device, the identified musical notes are synchronously output to a display device. User-specified parameters, adjustable at any time before, during or after the music-playing process, control frequency filtering, the graphic display of the identified musical notes and the graphical background on which the musical notes are displayed. Users may also utilize existing, or create their own, computer programming code software modules, known as plug-ins, or hardware components, to interface with the invention to extend and control the invention's functionality. Because the synchronous musical note identification and visualization process occurs extremely quickly, the method applies and works in real-time for live music.

The time required to send firmware update data to a printer or other peripheral device is shortened without changing the communication speed. A server sequentially reads records of source data in a first format, deletes blocks of consecutive blank data that are contained in the object data in records of the first format and are longer than the management data in a second format, and segments the object data before and after the blanks, connects the object data in records of the first format into units of a certain length, generates management data for the segmented object data and generates management data for the connected object data to produce target records in the second format, and sends the update data composed of the target records of the second format to the printer. Records of the first format written in ASCII code are binary converted, and binary records in the second format are sent to the printer.

A method and an apparatus are provided to remote boot a diskless computer on a WAN and the are disclosed. The remote boot apparatus is constructed as an embedded interface in the computer. The remote boot apparatus has a bi-directional buffer, a central processor, a network interface, a boot ROM and an interface core routine. The remote boot apparatus intercepts normal disk read of an MBR issued by a system BIOS of a personal computer, and then redirects the disk instruction in a form of TCP / IP packet to a boot server to read a corresponded file block from a location of the server. After the file block is received and confirmed by the computer, the received file block is unpacked and supplied to boot the computer.

A hearing aid comprises two microphones, directional processing means for combining the respective audio signals to form a spatial signal, a beamformer for controlling the directional processing means to provide adaptation of the spatial signal, and means for boosting low frequencies of the spatial signal. A feedback estimator generates a feedback compensation signal, which is combined with the boosted spatial signal. By applying feedback compensation only after directional processing and low frequency boosting, the device avoids interference by the feedback estimator with the function of the beamformer. The invention also provides a method of processing signals in a hearing aid.

Methods and systems are provided for controlling sound level of a computer system within a selected zone. In one embodiment, the sound level within an enclosed space is detected and an electronic signal representative of the sound level is generated in response. The presence of one or more person within the enclosed space is detected, and an electronic signal is generated responsive to the detected presence. The airflow rate and processor load are both decreased in response to the detected presence when the sound level exceeds a predefined sound-level setpoint.

A method and an apparatus are provided to remote boot a diskiess computer on a WAN. The remote boot apparatus is constructed as an embedded interface in the computer. The remote boot apparatus has a bi-directional buffer, a central processor, a network interface, a boot ROM and ail interface core routine. The remote boot apparatus intercepts a normal disk read of an MBR issued by a system BIOS of a local computer, and then redirects the disk instruction in a form of TCP / IP packet to a remote boot server to read a corresponding file block from a location of the remote boot server. After the file block is received and confirmed by the computer, the received file block is unpacked and supplied to boot the computer.

The invention provides a flight control method of a QUAV. The method comprises the following steps that S10) a dynamical model and a dynamic equation of the QUAV are established; and S20) a compound control based control manner is designed to control four independent control channels converted from the dynamic equation in the step S10), control manners for the four channels include height PID, tumbling ADRC, pitching ADRC and yaw EACS-PID respectively, and conversion of control quantities is controlled to adjust the rotating speed of the four rotors and further achieve attitude control. Via the method of the invention, the QUAV adapts to the external environment change, yaw EACS-PID can realize adaptive adjustment of control parameters, tumbling ADRC and pitching ADRC can resist to interference more actively, height PID can be used to maintain high anti-interference capability and robustness and avoid the process from being too complex, the processor load of the QUAV is reduced, and the operation efficiency of hardware is improved.

A method for using the waste heat of a computer system with a plurality of processors comprises the following steps. Jobs in the computer system are distributed to the processors in such a way that processors of a first group of processors are operated with a high processor load and processors of a second group of processors are operated with only a minimal processor load. In another method, waste heat is dissipated from the processors by a cooling device, wherein the waste heat dissipated from the processors is regulated in such a way that the processor assumes a temperature that is greater than a given minimum temperature. In both cases, the waste heat of the processors is transferred to a device for using the waste heat.

A method, apparatus, and system (48) are disclosed for use in synthesizing an audio performance (50) in which one or more acoustic characteristics, such as acoustic space, microphone modeling and placement, can selectively be varied. In order to reduce processing time, the system utilizes pseudo-convolution processing techniques (54) at a greatly reduced processor load. The system is able to emulate the audio output in different acoustic spaces, separate musical sources (instruments and other sound sources) from musical context; interactively recombine (56) musical source and musical context with relatively accurate acoustical integrity, including surround sound contexts, emulate microphone models and microphone placement, create acoustic effects, such as reverberation (58), emulate instrument body resonance and interactively switch emulated instrument bodies on a given musical instrument.

A bar code scanning system and method for scanning a bar code containing a key including successively scanning the bar code and providing, for each scan, a plurality of data elements forming a scan fragment for at least a portion of the bar code, identifying each fragment containing a portion of a reference key, detecting when there has been a match between a reference key and the identified key fragments, determining if a complete key has been constructed from the key fragments, calculating a displacement between the key fragments which constructed the complete key, and aligning data fragments of the bar code by placing each successive data fragment in alignment with the previous data fragment offset by the amount of the displacement.

To lighten the processing load of embedding a digital watermark in content data, a preliminary process (embedding strength map generating process) run by a preprocessing section and the main process (digital watermark embedding process) run by a man processing section are run mutually independently. Specifically, the preliminary process of the preprocessing section is run each time new content data is stored to the content data database, and the main process of the main processing section is run when a content delivery request is received from a receiving terminal (client).

A monitoring and control device for an aircraft actuator includes a control module, delivering control signals for the actuator and position signals for the actuator determined according to control messages received from a piloting management system of the aircraft, and at least one first position sensor supplying information concerning the position of the actuator, and a monitoring module, delivering position signals for the actuator and receiving the control signals received from the piloting management system of the aircraft, and information relating to the position of the actuator supplied by at least one second position sensor. The control and monitoring modules are capable of assessing the consistency of the signals processed therein and of controlling accordingly a power supply and disabling module of the actuator.

A method for displaying data objects based on social networks is executed by a cloud access system. The method comprises receiving view preference settings from a user of the cloud access system. The view preferences settings comprise group names and time periods. The method further comprises querying a friend list according to the group and polling data objects shared by the user and the friends according to the time period. Each of the shared data objects is renamed to its uploaded time, re-sorted according to the timeline and stored in memory. The polling cycle is determined according to degrees of activities of the user and the friends on social networking sites.

An electronic timepiece can easily acquire a leap second information reception time with minimal processor load. A first table groups leap second information reception times expressed by hour, minute, second, and day values into plural minute-second patterns of minute-second combinations that are common to plural hours, and relates numbers identifying these minute-second patterns to the day and hour values. The minute-second combinations are grouped by number in a second table. The number corresponding to the day and hour of the internal time is found from the first table (S1). A minute-second combination that is later than the internal time is found from the minute-second combinations corresponding to the acquired number (S2). And leap second reception time is calculated. If the resulting leap second reception time matches the internal time is determined (S9). If the times match, the leap second information is received (S10, S11).

A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.

A home network system and a method for controlling the same. The home network system includes one or more network managers or one or more master units to perform an operation control function and a state monitoring function of home appliances connected to the same network. In the case where the network managers or the master units each generate an operation control signal to perform an operation control function or a state monitoring function, and are connected to a new network or further connected to a typical network, the home network system automatically establishes network information, and performs a database (DB) synchronization function associated with changed network information, such that a variety of network configurations can be configured, resulting in increased control convenience.

A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.

Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.

The invention provides a multicast realizing method and apparatus for an edge network, and the multicast realizing method and apparatus are applied on an SDN controller of the edge network. The multicast realizing method includes that the inlet port of a downlink multicast protocol message of a multicast set reported by a network device serves as an uplink port of the multicast set on the network device, the inlet port of an uplink multicast protocol message of the multicast set reported by the network device serves as a downlink port of the multicast set on the network device, the topological structure of the multicast set in the edge network is generated according to the uplink port and the downlink port of the multicast set on the network device and the global topological structure of the edge network, the forwarding path of the multicast set in the edge network is determined according to the topological structure of the multicast set in the edge network, and flow meter for forwarding the multicast set flow is transmitted to the network device on a forwarding path. The processor load of the network device is reduced, and the performance of the network device is improved.

In a method for processor overload control in a wireless or other network, a processor occupancy level (“PO”) of a network processing unit is monitored and compared to a target PO. If the measured PO exceeds the target PO, one or more network load sources are controlled to reduce the data load of the processing unit, until the measured PO falls below a designated PO. “Load source” refers to a source of extant and / or potential data traffic through the processing unit, and / or a network control factor relating thereto, the control of which results in a reduction (or prevents an increase) in the data traffic handled by the processor. Examples include existing data flows, new calls, and BE flow window size. The load sources are controlled according to differentiated QOS levels, wherein non delay-critical data flows (e.g., BE flows) are reduced before delay-critical data flows, e.g., EF or AF flows.

In a method for controlling a measuring system in a chassis measuring station, the motor vehicle is detected automatically in the measuring station by at least one detection unit and its position is ascertained with respect to at least one measuring device which is controlled on the basis of a signal of the detection unit in that an operating state of the measuring device is activated. The measuring system includes at least two mutually opposite measuring devices, which respectively have one image acquisition unit and one transverse referencing unit, and at least one detection unit, which is a light barrier having at least one transmitter and receiver.

A transmitter includes generating unit configured to generate a feedback signal and an analyzing unit configured to analyze transmission quality in a time domain and in a frequency domain by using the feedback signal. The transmitter also includes an adapting unit configured to adapt the pre-distorter if the transmission quality is below the threshold.

Apparatus and method for data transmission while performing encoding processing on a non-limited moving vector mode, which avoids an increase in required memory capacity and a reduction in processing load, the apparatus comprising a two dimensional address generating unit for generating an access address of an external memory and an address control unit for administrating the horizontal position and the vertical position of the extended logical space and generating an operation authorizing signal for the two dimensional address generating unit, and the two dimensional address generating unit and the address control unit are operated in relation to each other so that an access address to outside the effective video data region is controlled to be an address of a pixel data at the periphery of the effective video data region, thereby reducing the extended region in the external memory.

An experimental design for motion estimation in video compression that reduces the number of search locations within a search window by selecting the search locations from a predefined orthogonal table. The search locations are then compared with a reference block to generate match-values that are used to generate level-values reflecting dispositional relationships of the search locations and the relative magnitudes of the match-values. A preliminary motion vector is generated according to the relative magnitudes of the level-values. Candidate results are also generated based on the match-values. A final motion vector is generated by applying predetermined formulas to the level-values and altering the preliminary motion vector according to the candidate results when indicated to do so by the results of the formulas.

The transmission server according to the present invention includes a processor, buffer memory, an I / O bus, and a transmission unit. Furthermore, the transmission unit includes a transmitting unit for controlling the generation and transmission of a packet, buffer memory for holding transmission data provided by the processor, and an NIC for connection to a network. The processor manages receivers, and transfers data in the buffer memory to be transmitted to the transmission unit connected to the I / O bus. The transferred data is stored in the buffer memory of the transmission unit. The transmission unit generates a packet for each receiver from the data in the buffer memory according to the receiver information, and transmits the data to a network through the NIC.

Time required sending firmware updates to a peripheral device, e.g., a printer, is shortened without changing the communication speed. A server sequentially reads records of source data in a first format, deletes blocks of consecutive blank data that are contained in object data in records of the first format and are longer than management data in a second format, segments the object data before and after the blanks, connects the object data in records of the first format into units of a certain length, generates management data for each of the segmented object data and connected object data to produce target records in the second format, and sends the update data composed of the target records of the second format to the printer. Records of the first format written in ASCII code are binary converted, and binary records in the second format are sent to the printer.