87results about How to "Reduce data load" patented technology

A liquid crystal display, including: a first substrate and a second substrate; a liquid crystal layer; a first data line disposed on the first substrate; a pixel electrode disposed on the first substrate; and a common electrode disposed on the first substrate and overlapping at least a portion of the pixel electrode and the first data line. One of the pixel electrode and the common electrode includes a plurality of branch electrodes spaced apart from each other and the other of has an at least approximately planar shape that is substantially parallel to a surface of at least one of the first substrate and the second substrate. The display can also include a passivation layer having a dielectric constant of about 3.5 or less, and including a first portion disposed between the common electrode and the first data line.

An apparatus for managing requests for media data such as video data for effecting rapid channel change in IPTV services comprises an interface for receiving data requests addressed for processing by a particular data request service device, and an agent operatively coupled to the interface and configured for selecting which of a number of different data request service devices to send the request, irrespective of the device to which the request is addressed. The apparatus includes a module for determining if a received request can be serviced by a preferred request service device based on its monitored ability to service the request. If the module determines that the preferred device is capable of servicing the request, the request is directed to that device, and otherwise to another device, which may be the device to which the data request is originally addressed. The preferred request service device may reside at an access node for delivering media services to subscriber equipment.

A method of and a system for synchronising a plurality of spaced apart nodes of a network to a reference time of a control centre, the method comprising receiving measurement data from each of the plurality of nodes; ranking the plurality of nodes with respect to one another according to the measurement data; selecting one or more master nodes from the plurality of nodes according to the ranking; assigning each of the plurality of nodes to a corresponding master node; determining a first time offset between the local time measured at each node and the local time measured at its corresponding master node and determining a second time offset between each of the master nodes and the reference time such that the time offset between the local time measured at each node and the reference time can be determined.

Methods and systems for reducing the overhead of validating constraints in a database are provided. The method includes providing a target table, and providing a source table. The source table includes data to be loaded into the target table. The method further includes loading data into the target table from the source table including eliminating any logic to validate a constraint defined on the target table based on one or more pre-determined conditions.

Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an isolation gate. A memory cell is selected in a selected subarray of a selected memory block, and a bit line of the selected memory cell is coupled to a corresponding local data line. Only a local data line of the selected subarray is coupled to the sense amplifier to perform a sense operation, and a global read data line is driven via a read driver in accordance with an output signal of the sense amplifier. A load of a sense node of the sense amplifier in a semiconductor memory device is reduced to implement high-speed reading of internal data.

Disclosed are a method of changing a connection state according to a movement of a UE and an apparatus for the same. The method of a UE includes: receiving indication information indicating a connection change into a specific RRC state from an evolved NodeB (eNB); configuring a connection state of the UE into the specific RRC state based on the indication information and performing a cell reselection operation according to a movement of the UE; and changing the connection state of the UE into an RRC idle state based on at least one piece of information on whether an RRC resume procedure is initiated, system information of a cell selected by the cell reselection operation, and radio access technology information, wherein the specific RRC state is a state distinguished from an RRC connection state and the RRC idle state.

A graphic display control system is disclosed. The graphic display control system comprises a server computer comprising a memory unit, a graphic display controller accessing image data displayed on the server computer and a cursor information and thereby storing the image data and the cursor information in the memory unit, a compression engine performing an image compression of the image data displayed on the server computer except a cursor pattern data of the cursor information to generate an compressed image data and thereby storing the compressed image data in the memory unit, a network controller receiving the compressed image data and the cursor information from the memory unit and transmitting the compressed image data and the cursor information through a network, and a remote client computer comprising a memory unit, a network controller receiving the compressed image data and the cursor information through the network and storing the compressed image data and the cursor information in the memory unit of the remote client computer, a decompression engine performing an image decompression of the compressed image data in the memory unit of the remote client computer to generate a decompressed image data and storing the decompressed image data in the memory unit of the remote client computer, a graphic display controller receiving the decompressed image data and displaying the decompressed image data on the remote client computer, and a cursor pattern overlay controller receiving the cursor information and overlaying the cursor information on the decompressed image data.

A data processing apparatus that is capable of improving the accuracy with which form types can be identified. An image file of a form and an additional file including a form type ID of the form are inputted. A character recognition process on the image file is carried out based on the form type ID. The image file and a result obtained in the character recognition process are stored in a storage device 103.

This invention discloses a base station TCP proxy confirmation method based on ARQ information and its system. The method includes sending/ receiving and processing the up and down data. The system includes a base station and a mobile station connected by radio links, in which, the base station includes a base station start up and control module, a sending and analyzing module, a base station segment and reassembling module, a proxy confirmation module and a receiving and analyzing module, the mobile station includes a start and control module, a segment reassembling module and a filter module, which increases the mobile rate of the TCP sending window and reduces the probability of timeout of TCP resulted in increasing transmission time delay by the data link layer ARQ.

The invention discloses a method, an application server, a network database and a system achieving a heartbeat mechanism. Security mechanisms are established in the application server and the network database. A mapping relation between user network layer identifications is established in the application server and the network database. When a network terminal user logs in the application server to activate business application through an application client, the heartbeat mechanism is established between the application server and the network database. By adopting the method, the application server, the network database and the system achieving the heartbeat mechanism, the transmission frequency of short databases between a network and a terminal can be effectively reduced, a network load is lowered, and in addition, the business process of the application business server is effectively simplified.

A display substrate includes a gate line, a gate insulating layer, a data line, a thin-film transistor (TFT), a storage line, a passivation layer, a color filter layer, a pixel electrode, a first light-blocking layer and a second light-blocking layer. The storage line includes the same material as the gate line. The passivation layer covers the data line. The color filter layer is formed on the passivation layer. The pixel electrode is formed on the color filter layer in each pixel. The first light-blocking layer is formed between adjacent pixel electrodes, and includes the same material as the gate line. The second light-blocking layer is formed between the first light-blocking layer, and includes the same material as the data line. Therefore, an aperture ratio may be increased.

A data processing system is provided comprising fetching logic for fetching program instructions for execution, a first data-accessing unit for handling decoding and execution of data access instructions and a second data-accessing unit for handling decoding and execution of program-counter-relative data access instructions. Handling of the program-counter-relative data access instructions by the second data-accessing unit is performed differently from the handling of the data access instructions by the first data-accessing unit.

The invention claims a method for testing a memory, comprising the steps as follows: aiming at a memory, generating random number data or generating testing data in specific format according to an algorithm by using the operation capacity of a controller after receiving a testing instruction and a program code sent by a testing computer; carrying out writing-in, reading-out and comparison operations of data on a flash memory; and delivering the test result to the testing computer. The testing speed of the memory is increased by greatly reducing the data input and output loads to the memory from the testing computer.

A driving substrate of an e-paper apparatus includes a first metal layer, a second metal layer and a pixel electrode. The first metal layer has a scan line and a first storage electrode. The second metal layer has a data line and a common line. The scan line and the data line are disposed crossingly. The common line is disposed parallel to the data line substantially. The common line and the scan line are disposed crossingly. The pixel electrode is disposed over the common line and is electrically connected to the first storage electrode through a via.

Data acquisition and automatic diagnosis is performed at test points by respective wireless monitoring units (WMU). Each WMU tests a first indicator periodically at a first rate to determine whether to test a full set of indicators. Evolution of the first indicator determines the pass/fail result of a reduced assessment of the corresponding test point. The pass/fail result is automatically sent off-site to a central database. When a fail occurs, a full assessment is performed, which includes monitoring the full set of indicators. Automatic diagnosis is performed based on the full set of indicators. The reduced assessment does not include automatic diagnosis of a test point, but is used to decide whether to perform the full assessment and automatic diagnosis. Results of the automatic diagnosis are sent to the central database. Raw data is not sent automatically.

A semiconductor device with an arithmetic processing function is provided. In the semiconductor device, an imaging portion and an arithmetic portion are electrically connected to each other through an analog processing circuit 24. The imaging portion includes a pixel array 21 in which pixels 20 used for imaging and reference pixels 22 used for image processing are arranged in a matrix, and a row decoder 25. The arithmetic portion includes a memory element array 31 in which memory elements 30 and reference memory elements 32 are arranged in a matrix, an analog processing circuit 34, a row decoder 35, and a column decoder 36.