178 results about "Network processing unit" patented technology

A method for routing and switching data packets from one or more incoming links to one or more outgoing links of a router. The method comprises receiving a data packet from the incoming link, assigning at least one outgoing link to the data packet based on the destination address of the data packet, and after the assigning operation, storing the data packet in a switching memory based on the assigned outgoing link. The data packet extracted from the switching memory, and transmitted along the assigned outgoing link. The router may include a network processing unit having one or more systolic array pipelines for performing the assigning operation.

A system and method of moving information units from an output flow control toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to service based on a weighted fair queue where position in the queue is adjusted after each service based on a weight factor and the length of frame, a process which provides a method for and system of interaction between different calendar types is used to provide minimum bandwidth, best effort bandwidth, weighted fair queuing service, best effort peak bandwidth, and maximum burst size specifications. The present invention permits different combinations of service that can be used to create different QoS specifications. The "base" services which are offered to a customer in the example described in this patent application are minimum bandwidth, best effort, peak and maximum burst size (or MBS), which may be combined as desired. For example, a user could specify minimum bandwidth plus best effort additional bandwidth and the system would provide this capability by putting the flow queue in both the NLS and WFQ calendar. The system includes tests when a flow queue is in multiple calendars to determine when it must come out.

A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.

In one embodiment, a network security appliance includes a logic circuit, a network processing unit, and a general purpose processor to protect a computer network from malicious codes, unauthorized data packets, and other network security threats. The logic circuit may include one or more programmable logic devices configured to scan incoming data packets at different layers of a multi-layer protocol, such as the OSI-seven layer model. The network processing unit may work in conjunction with the logic circuit to perform protocol parsing, to form higher layer data units from the data packets, and other network communications-related tasks. The general purpose processor may execute software for performing functions not available from the logic circuit or the network processing unit. For example, the general purpose processor may remove malicious code from infected data or perform malicious code scanning on data when the logic circuit is not configured to do so.

The invention discloses a unidirectional transmission internal and external network secure isolating gateway applicable to an industrial control network, belongs to the technical field of the industrial control network. The isolating gateway comprises an external network processing unit, a data ferry unit and an internal network processing unit; the external network processing unit is connected with the internal network processing unit through the data ferry unit; and the software and the hardware of the internal and external networks are isolated at the same time; the external network processing unit, the data ferry unit and the internal network processing unit are completely independent and communicate through a self-defined protocol. The isolating gateway is advantaged by that the isolating gateway is used for realizing unidirectional data transmission by the industrial control network and an upper computer public network under a physical isolating condition; identity authentication and content filter are controlled through a plug-in mode; and the reliability and the security of the industrial control network are ensured to the maximum extent.

A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a weighted fair queueing system where the position of the next service in a best efforts system for using bandwidth which is not used by committed bandwidth is determined based on the length of the frame and the weight of the particular flow. A “back pressure” system keeps a flow from being selected if its output cannot accept an additional frame because the current level of that port queue exceeds a threshold.

A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.

The invention provides a neural network processing unit and a processing system comprising the same. The processing unit comprises a multiplying unit module which comprises a multilevel structure forming an assembly line, and is used for executing the multiplying operation of to-be-calculated nerve cells and weight values in a neural network, wherein each level of the structure of the multiplyingunit module complete the suboperation of the multiplying operation of to-be-calculated nerve cells and weight values; and a self-accumulator module which carries out the accumulation of the multiplying operation result of the multiplying unit module based on a control signal, or outputs the accumulation result. The processing unit and the processing system can improve the calculation efficiency ofthe neural network and the resource utilization rate.

A data processing apparatus for registering image data includes a network processing unit configured for acquiring image data through a network, an image correction unit for analyzing the image data, extracting a background image and a subject image from the image data, and correcting the extracted background image according to a correction condition, and a database unit for storing the corrected image data such that the image data is associated with the corrected image data.

Systems and methods for processing media streams for transport over a network based on network conditions. An integrated circuit comprises a media processing unit coupled to receive feedback from a network processing unit. The media processing unit converts a media stream from a compressed input stream to a compressed output stream such that the compressed output stream has characteristics that are best suited for the network conditions. Network conditions can include, for example, characteristics of the network (e.g., latency or bandwidth) or characteristics of the remote playback devices (e.g., playback resolution). Changes in the network conditions can result in a change in the conversion process.

The invention provides a device and method for executing neural network calculation. The device comprises an on-chip interconnection module and a plurality of neural network processing modules which are in communication with an on-chip interconnection unit, and the neural network processing modules can read and write data from other neural network processing modules through the on-chip interconnection module. In multi-core multi-layer artificial neural network calculation, neural network calculation of each layer is required to be divided, then the neural network processing modules calculate,calculation result data of each layer is obtained, and multiple neural network processing units further conduct data exchange on the calculation result data of each layer.

An efficient conversion method for a deep learning model provided by the embodiment of the invention is used to solve the technical problem that the development efficiency and operation efficiency of a deep learning model are low. The method includes the following steps: building a data standardization framework corresponding to an NPU (Neural-Network Processing Unit) model according to a general deep learning framework; using the data standardization framework to convert the parameters of a deep learning model into the standard parameters of the data standardization framework; and converting the standard parameters into the parameters of the NPU model. According to the invention, a unified data standardization framework is built for a specific processor according to the parameter structures of general deep learning frameworks. Standard data can be formed using the unified data structure of the data standardization framework according to the parameters of a deep learning model formed by a general deep learning framework. Thus, the process of data analysis by the processor depends much less on the structure of the deep learning model, and the development of the processing process of the processor and the development of the deep learning model can be separated. A corresponding efficient conversion device is also provided.

The invention relates to an intelligent tracking flight system and method of a UAV, and belongs to the field of intelligent autonomous navigation of the UAV. The flight system comprises an image acquisition unit for image acquisition, a flight attitude measurement unit for detecting a flight inertia, a neural network processing unit for neural network processing and a control unit for control flight motion of the UAV; an image collected by a camera in the front of the UAV serves as input, the input is identified by the convolutional neural network, and an obstacle avoidance strategy is given.In the flight process, the alight attitude measurement unit based on a tunnel magnetic resistance effect characterized by high response is used to obtain key change position of the flight attitude ofthe UAV, the image acquisition unit is started to capture key images, a stereoscopic model of the flight environment is formed, key position images are provided for the UAV tracking flight path, and the integrated safety of the UAV tracking flight is improved.

The invention discloses an anomaly detection method and a system for a network processing unit. The method comprises the following steps: anomaly detection operating codes are added into execution processes of each thread of the network processing unit, and the network processing unit makes first marks on mark positions corresponding to the current thread in an anomaly protection mark data area in a shared memory when the network processing unit runs the anomaly detection operating codes of the current thread; when the cycle of a timer is up, a coprocessing unit detects all the mark positions in the anomaly protection mark data area, and the thread not corresponding to the mark positions of the first marks is abnormal if the fact that not all the mark positions are the first marks is detected; and the coprocessing unit can make second marks on all the mark positions if the fact that all the mark positions are the first marks is detected. Based on the characteristics of the process of the network processing unit software, the invention can effectively detect the anomaly of the thread in time, thereby greatly improving the failure detection capability of network equipment using the network processing unit as the core unit in the operating period.

There is provided a communication device which can search for a desired communication device and request a service, without being conscious of the status of the power supply of other communication devices on a network, and achieve a reduction in power consumption. A communication device 100 includes a main processing unit 110 to process main service provided for other communication devices, a network processing unit 120 to transmit and receive a request packet and a response packet among other communication devices, and an integrated power supply unit 150 to stop supplying power to the main processing unit 110 in a state of being able to supply it again and to supply the power to the network processing unit 120, wherein the network processing unit 120 is provided with an automatic responding unit 703 to determine whether or not it can respond to the received request packet only by itself and, when the response is possible, to transmit the response packet to the communication device, and a power supply controlling unit 704, when the response is not possible, to control a main-power supply unit 151 to supply the power to the main processing unit 110.

The invention provides a high speed regular expression matching hybrid system and method based on FPGA and NPU (field programmable gate array and network processing unit); the system is mainly composed of an FPGA chip and a multicore NPU; a plurality of parallel hardware matching engines are implemented on the FPGA chip, a plurality of software matching engines are instantiated on the NPU, and the hardware engines and the software engines operate in running water manner. In addition, a high speed RAM (random-access memory) on the FGPA chip and an off-chip DDR3 SDARM (double-date-rate three synchronous dynamic random-access memory) are used to construct two-level storage architecture; secondly, a regular expression rule set is compiled to generate a hybrid automaton; thirdly, state table items of the hybrid automaton are configured; fourthly, network messages are processed. The high speed regular expression matching hybrid system and method based on FPGA and NPU have the advantages that matching performance under complex rule sets is improved greatly, and the problem that the complex rule sets have poor performance is solved.