162 results about "Network processing unit" patented technology

The invention relates to the technical field of data security, can be applied to business scenes of financial science and technology, medical health and the like, and discloses a data encryption method, device, equipment and medium, comprising: acquiring a real-time state vector representing a running state of a chaotic neural network processing unit, monitoring a chaotic characteristic of the real-time state vector to generate a chaotic intensity index, and comparing the chaos intensity index with a preset chaos threshold value, generating an original key based on the real-time state vector when a key updating condition is met, dynamically adjusting a weight matrix of the chaos neural network processing unit according to the chaos intensity index, and performing cryptographic processing on the original key to generate a final key. And performing encryption processing on the target data by using the final key to generate target encrypted data. According to the method, the internal state of the chaotic neural network is used as a dynamic key generation basis, so that the dependence on an external entropy source and fixed parameters is eliminated, and the security and real-time performance of a data encryption process are improved.

The invention discloses a method for supporting fast switching of multiple models by NPU (Network Processing Unit) firmware. According to the invention, the system real-time performance and the resource utilization rate in a multi-task scene are obviously improved. Through a dynamic hierarchical caching strategy and a priority scheduling mechanism, the system can intelligently allocate cache resources and preferentially guarantee rapid loading of a high-frequency and high-urgency model, for example, in an automatic driving scene, switching delay of a path planning model can be reduced to a millisecond level, and non-perceptual switching of key tasks is guaranteed. The incremental parameter loading technology and firmware-level context management are deeply fused, only model difference data are transmitted, and hardware is utilized to accelerate and recover a calculation state, so that bandwidth waste caused by traditional full-amount loading is greatly reduced, the model switching efficiency of edge computing equipment is improved by more than 10 times when multiple tasks such as voice recognition and image processing are carried out in parallel, and the efficiency of the edge computing equipment is improved. And meanwhile, the calculation precision is kept lossless.

The invention relates to an NPU computing task scheduling method, device and equipment for a multi-mode SoC main control chip. The method comprises the following steps of: extracting task characteristic parameters of an NPU (Network Processing Unit) calculation task in a multimode SoC (System on Chip) main control chip, and establishing an initial scheduling time sequence table; computing resource partition division is carried out on the NPU computing unit, and a resource state matrix is established; an overlapping time sequence matrix is generated, and a Q-learning task optimization model is constructed; performing double-layer grouping sorting to generate a task allocation sequence; resource load calculation is carried out, a migration cost matrix is generated, task redistribution is executed, and a task redistribution result is obtained; and generating a global execution time sequence of the NPU calculation task, performing task scheduling on the NPU calculation task according to the global execution time sequence, and outputting task scheduling execution information. According to the method, the task execution delay and the resource utilization rate are balanced, the overall optimality of the scheduling scheme is ensured, and the response capability and the processing efficiency of the system to the burst task are improved.

The invention relates to the technical field of computer hardware and network communication, in particular to a high-speed I / O (input / output) virtualization server based on an FPGA (field programmable gate array) and a remote forwarding method.The high-speed I / O virtualization server comprises an FPGA chip, a network processing unit, an I / O protocol processing unit, a protocol conversion and scheduling unit, a time sequence and transaction management unit and a data buffering and flow control unit are integrated in the FPGA chip; the optical fiber Ethernet interface module comprises a physical layer interface and an MAC layer processing and network configuration interface; the local I / O interface module comprises a USB interface circuit, a serial port interface circuit, a PCIe interface circuit and an interface expansion connector; the power supply and monitoring module comprises a multi-path power supply management system, a state monitoring and diagnosis system and an LED indication system; according to the self-adaptive Baud rate detection circuit, the Baud rate can be accurately locked under the condition that data with less than two characters is received, the number of data bits, the type of a check bit and the length of a stop bit are automatically identified, and compared with a traditional microcontroller scheme, the self-adaptive Baud rate detection circuit has higher precision and higher detection speed.

The present disclosure relates to the field of artificial intelligence (AI) and quantum technologies, and provides a quantum error correction hardware decoder and a chip. The quantum error correction hardware decoder includes: a memory storing instructions, a neural network processing unit, and a processor in communication with the memory and the neural network processing unit; and wherein, when the processor executes the instructions, the processor is configured to cause the quantum error correction decoder to: obtain error syndrome information for an error syndrome measured due to an error occurring in a quantum circuit, decode, by the neural network processing unit, the error syndrome information based on a neural network model to obtain an output result of the neural network model, and determine error information based on the output result, the error information indicating a qubit in which an error occurs in the quantum circuit and a corresponding error type.

The invention discloses a heterogeneous Chiplet hybrid precision Transformer acceleration system based on an MRAM-SRAM (Magnetic Random Access Memory-Static Random Access Memory), which adopts a Chiplet block integration technology, gives full play to the modularization advantages of high yield and low cost of the Chiplet block integration technology, and internally integrates two types of heterogeneous calculation cores of MRAM calculation Chiplet and SRAM-NPU calculation Chiplet and two types of scheduling management Chiplet and data interaction Chiplet control units. In a Transform calculation process, an MRAM (Magnetic Random Access Memory) calculates a Chiplet to carry out approximate token relationship prediction in a self-attention mechanism, an SRAM-NPU (Synchronous Random Access Memory-Network Processing Unit) calculates the Chiplet to realize accurate attention calculation by utilizing a high-speed read-write characteristic of an SRAM (Static Random Access Memory) and a flexible calculation capability of the NPU, meanwhile, a scheduling management Chiplet coordinates calculation task allocation, and a data interaction Chiplet ensures efficient data flow; according to the acceleration system, optimal combination of different process node devices is realized through a Chiplet heterogeneous integration technology, and three dimensions of calculation efficiency, energy consumption and precision are balanced by combining the high-density low-power-consumption storage and calculation integrated advantage of an MRAM and high-precision calculation of an SRAM-NPU.

The invention provides an edge gateway computing power sharing method based on an MQTT protocol. An edge terminal sends a computing power request to an edge gateway through the MQTT protocol, wherein the computing power request comprises a computing task type identifier and a priority identifier; after receiving the computing power request, the edge gateway dynamically schedules heterogeneous computing resources of a built-in neural network processing unit (NPU) and a built-in central processing unit (CPU) according to a computing task type identifier and a priority identifier; and the edge gateway executes a corresponding calculation task by using the scheduled calculation resource, feeds back a processing result to the edge terminal initiating the request through an MQTT protocol, and synchronizes own calculation power state information.

Various example embodiments of a processing unit fault detection capability are presented. The processing unit fault detection capability may be configured to support detection of faults in processor cores of a processing unit based on arrangement of the processor cores to form a data processing pipeline and monitoring of the processor cores of the data processing pipeline based on monitoring of the data processing pipeline (e.g., based on propagation of heartbeat messages via the data processing pipeline). The processing unit fault detection capability may be configured to support detection of faults in processor cores of various types of processing units, such as central processing units (CPUs), graphics processing units (GPUs), network processing units (NPUs), or the like.

The invention provides an automatic learning engine device based on a packaging large model training platform, and the device comprises a unified access specification module which carries out the standardized training and reasoning parameter configuration through a YAML configuration template file; the multi-device support and parallel computing framework module is compatible with three hardware devices including a CPU (Central Processing Unit), a GPU (Graphic Processing Unit) and an NPU (Network Processing Unit), and supports two parallel computing frameworks including Accelerate and DeepSpeed; the training engine module adopts a three-layer architecture to realize task allocation, state monitoring and exception handling; and the training algorithm framework module is used for analyzing the running configuration file, carrying out data set splitting and data format conversion, supporting various fine tuning training methods and evaluating the model. According to the overall scheme, the technical threshold of large model fine adjustment is lowered, non-professional personnel can complete complex model training tasks through simple configuration, and popularization and application of the large model technology are promoted.

The invention provides an industrial multi-protocol heterogeneous real-time video collaborative analysis method. The method comprises the steps that a lightweight compiler is developed, an operator dependency graph analysis module is integrated, instruction-level parallelism of a neural network processing unit is predicted through a graph neural network, and optimization intermediate representation is dynamically generated; constructing a protocol classification graph neural network model, carrying out protocol type self-identification and streaming media metadata automatic extraction, and converting a heterogeneous video stream into a standardized frame sequence; designing a multi-agent reinforcement learning model, and generating an optimal scheduling strategy through offline simulation training by taking a neural network processing unit calculation unit utilization rate, a memory bandwidth occupancy rate and a task queue depth as state spaces; predicting a video key region by adopting a hybrid network, and performing resolution downsampling on a non-key region in combination with motion vector analysis; the hardware-level scheduling adopts time slice rotation preemptive scheduling, and time slices are dynamically distributed according to the priority of an algorithm.

A control chip is provided. A storage circuit includes a memory and a control circuit. The memory includes a first region and a second region. The first region stores command streams. The second region stores parameters. The control circuit accesses the memory. A neural-network processing unit (NPU) receives a destination block and performs a destination command stream corresponding to the destination block. In response to the destination command stream pointing to the second region, the control circuit or the NPU determines whether the destination command stream has access authority. In response to the destination command stream not having access authority, the control circuit does not read the second region. In response to the destination command stream having access authority, the control circuit reads the second region and provides the destination parameter stored in the second region to the NPU.

A neural network processing unit (NPU) includes a processing element array, a SRAM memory configured to store at least one data of the artificial neural network model processed in the processing element array; and an NPU scheduler configured to control the processing element array and the SRAM memory based on predefined operation order information of the artificial neural network model processed by the processing element array and the NPU scheduler is configured to reuse a memory address value in which an operation value of a first layer of a first scheduling is stored as a memory address value corresponding to an input data of a second layer of a second scheduling, which is a next scheduling of the first scheduling.

The invention provides a spatial diffraction optical neural network processor, and relates to the technical field of spatial diffraction. The spatial diffraction optical neural network processor comprises a light field signal input unit used for converting to-be-calculated data into an input light signal and transmitting the input light signal; the first spatial diffraction optical neural network processing unit and the second spatial diffraction optical neural network processing unit are symmetrically arranged and are used for receiving input optical signals to carry out optical field regulation and control operation and reflecting and outputting, and phase regulation and control units are integrated on the first spatial diffraction optical neural network processing unit and the second spatial diffraction optical neural network processing unit; each phase regulation and control unit is used for carrying out light field regulation and control operation on an input light signal; the phase regulation and control units integrated on the first and second spatial diffraction optical neural network processing units are arranged in a staggered manner so as to realize optical signal connection through a reflection law; and the photoelectric detector array is used for converting the input optical signal subjected to the optical field regulation and control operation of the first and second spatial diffraction optical neural network processing units into an electric signal.

The density and power consumption of modern integrated circuits, such as Graphic Processing Units (GPUs), Central Processing Units (CPUs), and Network Processing Units (NPUs) is growing rapidly, which necessitates designing advanced cooling systems. Existing solutions for characterizing and validating these cooling system are inadequate. A flexible, scalable Thermal Test Vehicle (TTV) is disclosed which is based on an array of power transistors, measurement / control circuitry, and onboard computer. The TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

A server-based-Network Operating System (NOS) disaggregated switch device system includes a server device having a server chassis, a switch connector that is accessible on the server chassis, and a Central Processing Unit (CPU) system that is housed in the server chassis, that is coupled to the switch connector, and that is configured to provide a Network Operating System (NOS). Server / switch cabling is connected to the switch connector. A switch device includes a switch chassis, a server connector that is accessible on the switch chassis and that is connected to the server / switch cabling, and a Network Processing Unit (NPU) system that is housed in the switch chassis, that is coupled to the server connector, and that includes a memory subsystem that is configured to be provided with a plurality of switch tables via the server / switch cabling and by the NOS provided by the CPU system in the server device.

The invention provides a neural network processing unit scheduling system and method, relates to the field of artificial intelligence accelerators, and can set a task progress register in a neural network processing unit for recording the task processing progress of the neural network processing unit for processing and calculating sub-tasks and exposing the task processing progress to a software layer. A scheduler and a global shared task queue can be arranged in the runtime module. The scheduler is used for scheduling the calculation subtasks to the neural network processing units, screening the slow processing units according to the task processing progress of the neural network processing units, determining the remaining subtasks which are not completed by the slow processing units, taking the remaining subtasks as the calculation subtasks again, and sending the calculation subtasks to the neural network processing units; and re-issuing to the idle neural network processing unit through the global shared task queue. Therefore, the remaining sub-tasks which are not completed by the low-speed processing unit can be re-issued to the idle neural network processing unit, so that idle computing resources can be avoided, and the processing efficiency is improved.

The invention relates to the technical field of cross of storage controllers and artificial intelligence acceleration, and discloses a large model reasoning system and method based on combination of a flash memory controller and an NPU (Network Processing Unit), and the large model reasoning system comprises the flash memory controller, the NPU and a flash memory array, the flash memory controller integrates a host interface module, a flash memory interface module, an independent AI acceleration interface module and an AI management engine, and the AI management engine autonomously completes NPU initialization, model weight direct loading, KV Cache hierarchical management, RAG knowledge base retrieval and model switching; the flash memory array is divided into a firmware partition, an AI special partition and a user storage partition, and different data storage requirements are met. According to the method, large model reasoning with low delay and low CPU dependence can be realized, and the model loading delay is reduced from 5-30 seconds to lt; after 500 milliseconds, the CPU occupancy rate of the host is reduced from 15-25% to lt; 2%, and concurrent operation of 4-8 models is supported. According to the invention, integration of storage and calculation is realized, and edge end, data center and mobile equipment scenes are adapted.

This on-vehicle relay device comprises: a network processing unit that performs processing in an on-vehicle network; a storage unit that stores setting information indicating the setting content of the processing performed by the network processing unit; an update unit that performs updating processing for updating the setting information in the storage unit; and a reflection unit that reflects the setting content indicated by the setting information in the processing performed by the network processing unit. The storage unit includes a first storage area for storing the setting information and a second storage area for storing predetermined information. The update unit can update the setting information without changing the predetermined information in the second storage area.

An apparatus and method are disclosed for a fabric interface of a processing entity (PE) within a PE array optimized for neural network computations. The fabric interface includes a channel extension circuit and a channel compression circuit. The channel extension circuit is configured to receive first data from another PE, extend the channel dimension of the first data to produce extended data with an increased dimension that aligns with the minimum data granularity of an associated memory, and store the extended data in the memory. Conversely, the channel compression circuit is configured to fetch second data from the memory, compress the channel dimension of the second data to obtain compressed data with a reduced dimension, and output the compressed data from the PE.

The application provides an epilepsy prediction system based on multi-element weighted joint recursion and graph attention network, which can be applied to the fields of biomedical signal processing and artificial intelligence technology. The system comprises a brain function imaging module configured to acquire electroencephalogram signal data of a target object under authorization of the target object; a processor comprising a multi-element weighted joint recursion processing unit configured to obtain a phase space trajectory vector of each channel of the electroencephalogram signal data according to the electroencephalogram signal data, construct a recursion graph according to the phase space trajectory vector of each channel, obtain a channel correlation coefficient between any two channels based on the recursion graph of each channel, and construct a weighted adjacency matrix representing the brain function of the target object according to the channel correlation coefficient between any two channels; and a graph attention network processing unit configured to perform spatiotemporal feature processing according to the weighted adjacency matrix and the electroencephalogram signal data and output an epilepsy seizure prediction result.

A mmWave communication network (1; 2) comprising a plurality of distribution nodes (DP1-DPn), each distribution node comprising: a plurality of N sectors (S1-S4), where N is an integer being at least three, each of the N sectors comprising a mmWave transceiver (4) arranged for mmWave communication with an adjacent distribution node; and a network processing unit (5) configured to route data traffic between sectors of the N sectors (S1-S4) of an individual distribution node such that the individual distribution node is in an operation mode of either: a default bridge mode in which data from any one of the N sectors (S1-S4) is routed to all other sectors (S1-S4); or a non-default bridge mode (B) in which data from one of the N sectors (S1-S4) is routed to a selected subset of the other sectors (S1-S4); wherein the number of sectors in the selected subset is I with 0 ≤ I ≤ N-2; wherein at least two distribution nodes of the plurality of distribution nodes (DP1-DPn) are in a non-default bridge mode (B).

The invention provides an operator fusion method and device, equipment and a medium, which are used for solving the technical problems of low fusion efficiency, poor applicability or overlarge calculation amount consumed by fusion when operator fusion is carried out in the related art, and the method comprises the following steps: obtaining a plurality of operators to be fused; for any operator, based on a processing function of a preset neural network processing unit (NPU), determining at least one target operator which can be fused with the operator in the plurality of operators; and fusing the operator and the at least one target operator into a combined operator and processing the combined operator by using the NPU.

A network device includes a storage device and a network processing unit (NPU). The storage device stores a mapping of address and port (MAP) information table, wherein the MAP information table includes a plurality of table entries that store a plurality of second internet protocol (IP) headers each complying with a second IP version. The NPU receives a first packet with a first IP header that complies with a first IP version different from the second IP version, and generates and forwards a second packet that includes a second IP header retrieved from the storage device and at least a portion of the first packet.

A network device includes a storage device, a central processing unit (CPU), a hardware acceleration circuit, and a network processing unit (NPU). The storage device stores program codes. The CPU loads and executes the program codes to deal with a control function of a network speed test. The hardware acceleration circuit provides hardware-accelerated packet forwarding. The NPU interacts with the control function performed by the CPU, and deals with processing of data packets used for the network speed test. Transmission of the data packets between the network device and another network device is performed through the NPU and the hardware acceleration circuit, without intervention of the CPU.

A network device includes a storage device, a central processing unit (CPU), a hardware acceleration circuit, and a network processing unit (NPU). The storage device stores program codes. The CPU loads and executes the program codes to deal with a control function of a network speed test. The hardware acceleration circuit provides hardware-accelerated packet forwarding. The NPU interacts with the control function performed by the CPU, and deals with processing of data packets used for the network speed test. Transmission of the data packets between the network device and another network device is performed through the NPU and the hardware acceleration circuit, without intervention of the CPU.

The invention discloses a network configuration method and device, related equipment, a storage medium and a computer program product, and is applied to the technical field of cloud computing. The method comprises the following steps: in response to an application request of a user for applying for a bare metal server, according to link layer discovery protocol information of a plurality of neural network processing units (NPUs) in a target bare metal server, respectively distributing network configuration information for the NPUs to obtain parameter plane network information of the target bare metal server; updating a configuration drive file of the target bare metal server based on the parameter surface network information; and controlling the target bare metal server to execute the configuration drive file, and triggering the target bare metal server to perform network configuration on the plurality of NPUs when the configuration drive file is executed.

The invention discloses an ultra-low background measurement device and method for discriminating beta and gamma, and relates to the field of pulse discrimination and ultra-low background measurement. The liquid scintillator outputs fluorescence through radiation of the radioactive source; the high-speed photomultiplier performs photoelectric conversion on the fluorescence and outputs a high-speed current pulse signal; the data processing unit converts the high-speed current pulse signal into a high-speed voltage pulse signal, carries out direct bias and gain adjustment, and carries out analog-to-digital conversion to obtain a digital signal; the main control unit preprocesses the digital signal, and performs feature processing and pulse position adjustment on the preprocessed digital signal to obtain pulse feature data; a built-in convolutional neural network in the neural network processing unit determines a discrimination result about beta and gamma according to the pulse characteristic data and the digital signal; and the main control unit carries out gamma background elimination according to a discrimination result so as to realize ultra-low background measurement. According to the invention, pulse discrimination is carried out rapidly and accurately, so that the background is eliminated, and ultra-low background measurement is realized.

The invention relates to the technical field of avionics communication. The invention provides an airborne satellite communication processing terminal. The airborne satellite communication processing terminal comprises a data control unit, a satellite data processing unit and a network processing unit, the satellite data processing unit sends data sent by a satellite to the data control unit; the data control unit performs communication protocol analysis and data format conversion on the received data; the data control unit sends the data subjected to communication protocol analysis and data format conversion to the network processing unit; the network processing unit encapsulates the received data into an Ethernet frame and then sends the Ethernet frame to the built-in network; the built-in network sends the received data to the data control unit through the Ethernet communication interface; and the data control unit encrypts the received data, converts the encrypted data into satellite signals and sends the satellite signals to a satellite. Satellite communication is converted into a universal Ethernet communication interface, and the compatibility problem of multi-platform interfaces is solved.

The application discloses a network configuration method and device, related equipment, a storage medium and a computer program product, and applies to the technical field of cloud computing. The method comprises the following steps: in response to an application request of a user applying for a bare metal server, network configuration information is respectively allocated to a plurality of neural network processing units (NPUs) in a target bare metal server according to link layer discovery protocol information of the plurality of NPUs, and parameter plane network information of the target bare metal server is obtained; based on the parameter plane network information, a configuration driver file of the target bare metal server is updated; and the target bare metal server is controlled to execute the configuration driver file, and the configuration driver file triggers the target bare metal server to perform network configuration on the plurality of NPUs when being executed.

The novel network isolation data processing system comprises a plurality of network isolation password board cards which are connected in parallel, and each network isolation password board card comprises an internal network processing unit based on a trusted CPU, a multi-channel isolation processing unit based on an FPGA and an external network processing unit based on the trusted CPU. According to the invention, by deploying a plurality of physical isolation board cards and a data processing task scheduling mechanism, stable and reliable work can still be realized under the condition that a certain unit fails, and the problem of single-point failure of common network isolation equipment is effectively solved; the power consumption of the network isolation password equipment is reduced by combining a low-power-consumption mode of an isolation board card chip, the service life of the equipment is prolonged, and the trend requirement of strict data secrecy of a data system is met. The application of the invention has good social benefits and application prospects, and can promote the development of the network isolation data encryption technology in the field of information security to a certain extent.