15results about How to "Reduced package area" patented technology

The invention provides a three-dimensional photoelectric integrated packaging structure and a preparation method thereof, and the packaging structure comprises a TSV substrate, a rewiring layer, a first electric chip, a second electric chip, a dielectric layer, a conductive column, an optical chip module, a 3D stacked chip, and a horizontal storage chip. The optical chip module, the first electric chip and the 3D stacked chip are connected through the TSV substrate and the rewiring layer to form the optical integrated circuit, and the 3D stacked chip, the second electric chip and the horizontal storage chip are connected through the TSV substrate and the rewiring layer to form the electric integrated circuit, so that the transmission distance between the optical integrated circuit and the electric integrated circuit is shortened; the packaging area is reduced, the power consumption is reduced, and high-density integrated packaging of the photoelectric chip is realized.

The invention provides a preparation method of a 3DIC photoelectric integrated semiconductor packaging structure, and the method comprises the steps: carrying out the integrated packaging of an optical chip module, a 3D stacked chip and a horizontal storage chip through a TSV substrate, a rewiring layer, a first electric chip, a second electric chip, a dielectric layer and a conductive column, enabling the optical chip module to be connected with the 3D stacked chip through the first electric chip, enabling the optical chip module to be connected with the 3D stacked chip through the second electric chip, and enabling the optical chip module to be connected with the horizontal storage chip through the second electric chip; and the 3D stacked chip is connected with the horizontal storage chip through the second electric chip, so that short-distance connection between the optical integrated circuit and the electric integrated circuit is realized, the transmission distance of photoelectric signals is greatly reduced, the packaging area is reduced, the power consumption is reduced, and high-density integrated packaging of the photoelectric chip is met.

The invention belongs to the technical field of microwave integrated circuit chip design, and discloses an integrated passive device filter based on a TGV process. The integrated passive device filter comprises a GSG signal port, a three-dimensional inductor and a capacitor. The dielectric substrate is made of a glass material, so that the dielectric loss of the device can be reduced; a three-dimensional inductance structure mode is adopted, so that the Q value of the filter can be improved; a physical symmetric structure is adopted, so that cross mixing coupling of non-adjacent resonant circuits is easy to realize to improve out-of-band rejection performance; the integrated passive device is realized in a TGV process mode, high integration and miniaturization can be realized, the integrated passive device can be integrated in a radio frequency receiving and transmitting module in a chip flip-chip bonding or bonding mode, the packaging area and the wiring length are reduced, and meanwhile, the signal delay and the power consumption are reduced.

The embodiment of the present invention provides a wafer-level packaging structure of a MEMS microphone, comprising: a first silicon substrate, a second silicon substrate and an ASIC chip; the first silicon substrate is sealed and connected to the second silicon substrate; the ASIC chip is arranged on a side of the second silicon substrate away from the first silicon substrate; the second silicon substrate comprises a first region and a second region surrounding the first region; the first region comprises a plurality of blind holes; the first silicon substrate comprises a through-hole region, the through-hole region is arranged opposite to the first region; a back electrode and a diaphragm are arranged on a side of the first silicon substrate adjacent to the second silicon substrate, the back electrode and the diaphragm at least cover the through-hole region, and the back electrode is arranged on a side of the diaphragm adjacent to the second silicon substrate; the back electrode is electrically connected to the ASIC chip via a first lead arranged in the second region, and the diaphragm is electrically connected to the ASIC chip via a second lead arranged in the second region. The wafer-level packaging structure of a MEMS microphone provided by the embodiment of the present invention can reduce the packaging area of ​​the MEMS microphone, and meet the market demand for miniaturized packaging of MEMS microphones.

A multi-chip packaging structure comprises a chip embedded substrate, an integrated circuit (IC) chip, a conductive structure and a packaging layer. The chip-in-chip substrate has a first surface and a second surface which are opposite to each other. The chip-in-chip substrate includes a first rewiring layer, a second rewiring layer and a first power chip. The first rewiring layer is adjacent to the first surface and exposed on the first surface, and the second rewiring layer is adjacent to the second surface. The first power chip is arranged between the first rewiring layer and the second rewiring layer and is electrically connected with at least one of the first rewiring layer and the second rewiring layer. The IC chip is electrically connected to the second surface of the chip-embedded substrate in an insulated manner. The conductive structure is electrically connected with the IC chip and the chip-embedded substrate. The packaging layer wraps the IC chip and at least part of the conductive structure. According to the multi-chip packaging structure, the reliability, the electrical property and the thermal conductivity of the element can be effectively improved, the packaging design freedom degree is increased, and product miniaturization is achieved.

The utility model discloses a chip packaging structure of a composite through hole adapter plate, and belongs to the technical field of semiconductor packaging. The metal rewiring layer III (430) comprises a silicon through hole pinboard monomer (10) and a low-density plastic package through hole (310) which form a composite through hole pinboard, and the metal rewiring layer II (420) is in telecommunication connection with the metal rewiring layer III (430) through a high-density silicon through hole (110) and the low-density plastic package through hole (310) respectively; the high-density pin chip (61) is packaged above the high-density silicon through hole (110), and the low-density pin chip I (63) and / or the low-density pin chip II (65) are / is packaged above the low-density plastic package through hole (310) and are / is fixedly connected with the metal rewiring layer III (430) in a telecommunication mode. The structure integrates the low-density pin chip and the high-density pin chip at the same time, and has good compatibility.

The present invention discloses a three-dimensional packaging structure of an optoelectronic chip with an optical interconnection interface, comprising: an optical chip, one end of which is provided with an optical interconnection structure and a groove; a conductive through hole, which runs through the optical chip; a first wiring layer, which is arranged on the front side of the optical chip and is electrically connected to the conductive through hole; a second wiring layer, which is arranged on the back side of the optical chip and is electrically connected to the conductive through hole; an electric chip, which is arranged above the front side of the optical chip and is electrically connected to the first wiring layer; a cover plate, which is arranged above the optical interconnection structure and the groove of the optical chip; a plastic sealing layer, which integrally seals the front side of the optical chip, the electric chip and the cover plate; and an external solder ball, which is arranged below the back side of the optical chip and is electrically connected to the second wiring layer.

The present application proposes a chip packaging component and a chip function execution method thereof, wherein the chip packaging component comprises a plurality of pins, wherein a pin among the plurality of pins is used to receive a voltage signal. A processing circuit is used to receive the voltage signal, and the processing circuit determines whether the voltage level of the voltage signal is a first level or a second level, so as to generate a first control signal according to the first level, and generate a second control signal according to the second level. A first function circuit among the plurality of function circuits executes a first function according to the first control signal, and a second function circuit among the plurality of function circuits executes a second function according to the second control signal.

The invention provides a packaging structure and electronic equipment, and the structure comprises a plurality of chips which are laminated and are arranged in an insulating manner; the packaging piece is used for packaging the plurality of chips, and a plurality of via holes are formed in the packaging piece; and a plurality of conductive patterns, the plurality of conductive patterns are respectively filled in the plurality of via holes, and each chip is connected with at least one conductive pattern. According to the invention, the chips are arranged in a laminated manner, and the packaging height is increased and the packaging area of the integrated circuit is reduced by adopting a plastic packaging material through hole process with lower cost, so that the utilization rate of the number of the packaged chips is increased.

The utility model relates to the technical field of SD NAND, and particularly discloses an SD NAND based on a substrate type packaging structure, which comprises a substrate, a plurality of rows of substrate fingers are arranged on the surface of the substrate, and one row of substrate fingers are arranged at the edge of the substrate; the controller chip is arranged on the substrate, and a bonding pad of the controller chip is electrically connected with other substrate fingers on the substrate through bonding wires; the dummy chip is fixed on the substrate and is positioned on one side of the controller chip; the memory chip is fixed on the dummy chip and located above the controller chip, and a bonding pad of the memory chip is electrically connected with a substrate finger located at the edge of the substrate through the bonding wire; according to the SD NAND, the number of substrate fingers arranged on the periphery of a memory chip can be effectively reduced, so that the overall packaging area of the SD NAND is effectively reduced.

The utility model discloses a kind of power modules, including circuit board assembly and power chip assembly;Wherein, circuit board assembly includes first circuit board, third circuit board and the second circuit board being arranged between the two, power chip assembly includes the first power chip being arranged between first circuit board and second circuit board and the second power chip being arranged between third circuit board and second circuit board;Second circuit board is equipped with metal component, first power chip and second power chip are electrically connected with the metal component;First circuit board is equipped with the first insulating heat-conducting component for the heat dissipation of first power chip, and third circuit board is equipped with the second insulating heat-conducting component for the heat dissipation of second power chip.The power module of the utility model has the advantages of small packaging area and low parasitic effect.

According to the photoelectric system packaging structure and the preparation method thereof provided by the invention, the complete photoelectric system packaging structure can be formed through the arrangement of the 3D stacked logic storage module, the storage module, the optical module, the rewiring layer, the metal columns, the ASIC chip and the TSV composite adapter plate, the transmission distance of each module can be shorter, the signal transmission is faster, and the reliability of the photoelectric system packaging structure is improved. Transmission power consumption is effectively reduced, and the packaging area is reduced.

The invention discloses a patch type fuse with a voltage transient suppression function and a preparation method thereof, and the method is characterized in that the method comprises the steps: providing a substrate; a voltage transient suppressor and a fuse are fabricated on the substrate such that the voltage transient suppressor and the fuse are connected in series. According to the invention, the voltage transient suppressor and the patch type fuse are integrated in the same structural body to be manufactured and packaged together, so that the time for independently manufacturing two traditional devices is saved, the packaging area is saved, the packaging device is upgraded, the packaging processing efficiency is improved, and the labor cost is reduced.

The application relates to a packaging substrate structure for realizing inter-chip direct interconnection, comprising: a substrate; a first dielectric layer; a first chip, the front surface of the chip being embedded in the first dielectric layer, the first chip being provided with a first pad and a second pad with a size larger than the first pad; a second dielectric layer; a first metal through hole penetrating through the second dielectric layer and being electrically connected with the second pad; a second metal through hole penetrating through the second dielectric layer and the first dielectric layer and being electrically connected with a substrate pad; a third dielectric layer; a third metal through hole penetrating through the third dielectric layer and the second dielectric layer and being electrically connected with the first pad; a fourth metal through hole penetrating through the third dielectric layer and being electrically connected with the second metal through hole; wherein the top surfaces of the third metal through hole and the fourth metal through hole and the upper surface of the third dielectric layer are all provided with pads; and a second chip is flip-chip soldered on the pads on the top surface of the third metal through hole and the upper surface of the third dielectric layer.

The invention provides a display panel, a manufacturing method thereof and a display device, and relates to the technical field of display, the manufacturing method comprises the steps that an array substrate is provided, the array substrate comprises a display area and a hole area, and the hole area is surrounded by the display area; forming a light-emitting film layer on the array substrate; a first packaging layer is formed on the side, away from the array substrate, of the light-emitting film layer; etching the light-emitting film layer and the first packaging layer, and removing the parts of the light-emitting film layer and the first packaging layer in the hole region; a second packaging layer at least covering the light-emitting film layer and the etching section of the first packaging layer is formed on the side, away from the array substrate, of the first packaging layer and on the array substrate with the exposed hole area. The manufacturing method provided by the invention is beneficial to improving the use performance and the processing performance of the display device.