2results about How to "Reduced package area" patented technology

The utility model discloses a kind of power modules, including circuit board assembly and power chip assembly;Wherein, circuit board assembly includes first circuit board, third circuit board and the second circuit board being arranged between the two, power chip assembly includes the first power chip being arranged between first circuit board and second circuit board and the second power chip being arranged between third circuit board and second circuit board;Second circuit board is equipped with metal component, first power chip and second power chip are electrically connected with the metal component;First circuit board is equipped with the first insulating heat-conducting component for the heat dissipation of first power chip, and third circuit board is equipped with the second insulating heat-conducting component for the heat dissipation of second power chip.The power module of the utility model has the advantages of small packaging area and low parasitic effect.

The application relates to a packaging substrate structure for realizing inter-chip direct interconnection, comprising: a substrate; a first dielectric layer; a first chip, the front surface of the chip being embedded in the first dielectric layer, the first chip being provided with a first pad and a second pad with a size larger than the first pad; a second dielectric layer; a first metal through hole penetrating through the second dielectric layer and being electrically connected with the second pad; a second metal through hole penetrating through the second dielectric layer and the first dielectric layer and being electrically connected with a substrate pad; a third dielectric layer; a third metal through hole penetrating through the third dielectric layer and the second dielectric layer and being electrically connected with the first pad; a fourth metal through hole penetrating through the third dielectric layer and being electrically connected with the second metal through hole; wherein the top surfaces of the third metal through hole and the fourth metal through hole and the upper surface of the third dielectric layer are all provided with pads; and a second chip is flip-chip soldered on the pads on the top surface of the third metal through hole and the upper surface of the third dielectric layer.