129results about How to "Reduced package area" patented technology

The invention relates to an MEMS sensor encapsulation structure and an encapsulation method thereof, which are used for encapsulating an MEMS sensor. The MEMS sensor encapsulation structure is characterized by comprising a ceramic base, a side wall and a top cap, wherein a plurality of metal bonding pads are respectively arranged on a top layer and a bottom layer of the ceramic base; the metal bonding pads on the top layer of the ceramic base are connected with leads of the MEMS sensor; the MEMS sensor is arranged on the ceramic base; the metal bonding pads on the bottom layer of the ceramic base are connected with an external circuit; the ceramic base adopts one-layer or multi-layer perpendicularly interconnected structure; the side wall and the top cap are both made of kovar alloy. According to the invention, the ceramic base of which coefficient of thermal expansion is approximate to that of the MEMS sensor material is selected as the encapsulation material, in order to reduce influence of the base expansion stress to the MEMS sensor; meanwhile, the ceramic base can be utilized to realize one-layer perpendicular interconnection or multi-layer perpendicular interconnection; the system-level integration between the MEMS sensor and the peripheral circuit can be realized within a small area; high-density system-level encapsulation can be realized; the encapsulation flexibility and the expansibility of the MEMS sensor can be realized.

The invention discloses a super-high-density LED display device which comprises a substrate and an LED chip array packaged on the substrate. The chip array comprises a plurality of LED chips distributed evenly at intervals. By means of the Fan-Out Wafer-Level Package (FOWLP) process, the packaging area is narrowed, and the resolution ratio of an LED display screen is increased; all the LED chips are the same in structure, light-emitting wave band and type, the LED chips emit red light, green light and blue light after being coated with red light fluorescent powder, green light fluorescent powder and blue light fluorescent powder in a chip light-emitting curing mode respectively, and therefore it is ensured that the LED chips are consistent in light attenuation in the use process, and the development performance of the display screen is improved; pixel point distances can be smaller than 1 mm and even smaller than 0.1 mm, better performance such as high integrity, high resolution and consistent light color of the LED display device is achieved, and the super-high-density LED display device is importantly applied to indoor high-density display screens, projection devices and wearable display devices.

The invention provides a chip provided with a multiplex pin. The chip comprises the multiplex pin. When the multiplex pin is applied to another pin besides a test pin, voltage of the multiplex pin is larger than first threshold voltage or smaller than second threshold voltage. When the voltage of the multiplex pin is smaller than the first threshold voltage and larger than the second threshold voltage, the chip is in a test mode, and at the moment, the multiplex pin serves as the test pin and the first threshold voltage is larger than the second threshold voltage. Compared with the prior art, the chip is provided with the multiplex pin, whether the multiplex pin serves as the test pin is confirmed through testing of the voltage of the multiplex pin. The multiplex pin can serve as other pins, so the number of pins of the chip is reduced and a packaging area is reduced.

A method for driving a liquid crystal display capable of reducing power consumption, decreasing a packaging area or a number of packaged parts, and providing an image of high quality. Digital video data is output, with or without data being inverted, based on a polarity signal being inverted in every one horizontal sync period or in every one vertical sync period. A plurality of gray scale voltages is selected having either a positive or negative voltage. Any one of the plural gray scale voltages is selected based on digital video data, with or without inversion of a polarity of gray scale voltages. The selected one gray scale voltage is applied as a data signal to a corresponding data electrode.

The invention discloses a low temperature co-fired ceramic-based micro-electromechanical system (MEMS) packaging method. The method comprises the following steps of: preparing an upper low temperature co-fired ceramic substrate and a lower low temperature co-fired ceramic substrate respectively and forming a three-dimensional electrically-interconnected network, an embedded micro-channel and an open cavity in the upper substrate and/or the lower substrate; aligning the upper substrate with the lower substrate for packaging, packaging components and parts in the cavity and communicating the micro-channel with the cavity and the outside of a packaged body; and connecting an external micro-tube to the outlet of the micro-channel, which leads to the outside of the package body, and realizing gas or liquid flow between the cavity and the outside through the external micro-tube. The method has the advantages of improving the integration level, the stability and the flexibility of MEMS packaging, realizing vacuum packaging and heat dissipation of the components and parts in the cavity by conveying a circulating radiating medium through the micro-channel and conveying detection samples and the like to medical, biological or chemical MEMS components and parts in the packaging cavity through the micro-channel.

The invention provides a package-on-package structure of a chip and a package-on-package method. In the package-on-package structure, an electrode is leaded out through an interconnector and a first rewiring member in packaging a first layer of pipe cores. The package-on-package structure and the package-on-package method are suitable for packaging the chip with relatively high pad spacing. Furthermore no bonding lead is required and a packaging resistance is reduced. Furthermore a penetrating member which penetrates a first packaging member and a substrate is used for leading the electrode on a second layer of the chip out, thereby realizing chip packaging in a package-on-package manner, effectively reducing the packaging area of an integrated circuit and number of pins.

The invention discloses a color-temperature-adjustable COB packaging structure and a packaging method thereof. The color-temperature-adjustable COB packaging structure comprises a packaging substrate, CSP chip scale packaging devices, LED chips and a florescent glue sealing layer. The CSP chip scale packaging devices and the LED chips are fixed on the packaging substrate and wrapped by the florescent glue sealing layer. The florescent glue sealing layer is internally provided with at least one CSP chip scale packaging device and the LED chip, wherein the CSP chip scale packaging devices comprise chips and florescent glue wrapping the chips. The florescent glue and the florescent glue sealing layer are different in phosphor concentration. Light emitted by the CSP chip scale packaging devices and the LED chips passes through different numbers of phosphor powder particles and then color of different color temperature is obtained. The effect of color temperature adjustment can be achieved by controlling driving current in the CSP chip scale packaging devices and the LED chips.

An image sensor package structure is proposed, in which an image sensor is fixed on a substrate having metallization traces and an adhesion layer. Electric paths of the package structure are changed from the COG (chip on glass) process to the CIS (CMOS image sensor) process to improve electric characteristics. Moreover, spacers are formed at appropriate positions to prevent glue overflow from contaminating the sensing regions and solder balls. The proposed package structure can also shrink the package area to greatly enhance the yield and quality.

The invention relates to a multi-chip wafer level fan-out type three-dimensional package structure, comprising at least two rewiring layers, wherein the rewiring layers are dielectric layers, metal connecting structures connected with two sides to match each other and form interconnecting structures are provided on two sides of the dielectric layers, the metal connecting structures expose the dielectric layers to form metal contacts, a plastic sealing layer is arranged on one side of the rewiring layers, chips or passive elements are packaged in the plastic sealing layer, and the adjacent rewiring layers are connected by micro silicon blocks. The invention also discloses a packaging process for the multi-chip wafer level fan-out type three-dimensional package structure. By adopting the design scheme, passive devices of different sizes can be simultaneously integrated and packaged with bare chips, so that the degree of integration is greatly improved, the packaging process is particularly suitable for application of wifi, PA, PMU and the like using a large number of passive devices, and at the same time, the three-dimensional stacking method greatly reduces the packaging area.

The invention relates to a package of light-sensitive element and relative production. Wherein, it comprises: mounting light-sensitive chip on the base plate; clearing the contaminant; then using adhesive to mount a transparent sealing cover with chamber above the base plate, to cover the chip; therefore, it can clear the contaminant, improve the yield and reduce the packing area; in addition, the invention can arrange connecting part above the base plate and sealing cover to support connection.

The invention provides an RPMC-comprising (replay protection monotonic counter-comprising) enhanced flash chip and a packaging method thereof. The RPMC-comprising enhanced flash chip comprises a flash, an RPMC, and a memory chip, wherein the flash and the RPMC are packaged together and the memory chip is connected with the RPMC. Both the flash and the RPMC comprise respectively independent controllers. Same IO (input and output) pins in the flash and the RPMC are interconnected and are connected to a same external shared pin of the chip. Both the flash and the RPMC further comprise internal IO pins. The RPMC and the memory chip further comprise signal transmission IO pins. By the RPMC-comprising enhanced flash chip, the problems of high complexity, long cycle, high cost and large chip area in chip design are solved.

The invention discloses a circuit module and a manufacturing method thereof. The circuit module comprises a printed circuit board, a package chip and a switch tube, wherein the package chip and the switch tube are arranged on the printed circuit board, the package chip comprises a chip, a first plastic package layer and a plurality of metal posts, the first plastic package layer covers the chip, each metal post comprises a first end and a second which are opposite to each other, the first end is in contact with the chip, and the second end is exposed out of the first plastic package layer. Thepackage chip in the circuit module employs the metal posts to external electrical connection, so that the package area is reduced, and the reliability is improved.

A vibratory device includes an elastic plate and a piezoelectric diaphragm. The elastic plate includes a fixable portion, a vibratory portion, and a connection portion. The fixable portion is fixed to a fixation member. The vibratory portion is spaced away from a fixable surface of the fixable portion that faces the fixation member and arranged substantially in parallel with the fixable surface. The connection portion connects a first end of the fixable portion in its planar direction and a first end of the vibratory portion in its planar direction. The piezoelectric diaphragm is disposed on a surface of the vibratory portion that is adjacent to the fixable portion. In a direction N normal to the surface of the vibratory portion adjacent to the fixable portion, at least part of the second piezoelectric diaphragm does not overlap the fixable portion.

The invention discloses an integrated circuit chip with programmable functions and features and its operating method, wherein a one-time programmable (OTP) memory is used to realize the function of a non-volatile memory. The OTP memory may be based on multi-state fuses and gate oxide fuses. Because the OTP memory is very small, it occupies a smaller package area than metal fuses. In addition, since OTP memory can be implemented as part of a standard CMOS process, this approach is less costly and less complex than using electrically erasable programmable read-only memory (E2PROM).

The invention discloses a reading circuit of a non-refrigeration infrared focal plane detector and a method for improving the yield. An effective element circuit array is subjected to row gating and column integration through a control module, and a substitute signal is obtained according to the fault signal of the effective element circuit. Effective element resistors and fault effective elementresistors of adjacent rows are connected in parallel, so that the fault effective element circuit works normally, and the image elements of infrared images can be restored in real time. Further, a substitute signal is obtained according to the fault signal of a blind element or a reference element circuit, the adjacent blind element or reference element resistor and fault blind element or reference element resistor are connected in parallel, so as to restore the blind element circuit or reference element circuit. The problem of damaged column line or damaged row line of an infrared focal planeis solved.

The invention relates to a gold-wire-free encapsulation method of a large power white light LED part and a white light LED part, which belong to the field of the semiconductor luminous part, and comprise a chip is electrically connected with an outer lead bracket electrode, a fluorescent material layer is arranged at one side of the chip, a mono-crystal fluorescent material layer is adopted to form the fluorescent material layer, a transparent conductive film is prepared on the surface of the mono-crystal fluorescent material layer, a conductive metal electrode is arranged on the transparent conductive film, a mono-crystal fluorescent material wafer which carries the transparent conductive film and the conductive metal electrode forms a mono-crystal fluorescent material composite-functionunit, the mono-crystal fluorescent material composite-function unit is encapsulated with the chip through an eutectic welding way, and an electric connection channel is established between a pn electrode of the chip and the outer lead bracket electrode. By adopting the surface contact-type electric connection, the encapsulation reliability of the white light LED part is improved, the service lifeof the LED is remarkably prolonged, and the light-emitting efficiency is improved. The method is particularly applicable to the mass integration encapsulation production process and can effectively reduce the manufacturing cost of the LED luminous part.

The invention relates to a three-dimensional fan-out type integrated packaging structure. The integrated packaging structure comprises at least two re-wiring layers which are dielectric layers; metalconnecting structures for connecting the two sides for mutual matching to form an interconnection structure are arranged on the two side layer surfaces of the dielectric layers; the metal connecting structures expose the dielectric layers to be used as metal contacts; plastic packaging layers are arranged on one sides of the re-wiring layers; chips or passive elements are plastically packaged in the plastic packaging layers; and the adjacent re-wiring layers are connected through metal conductive columns. The invention also discloses a packaging process of the three-dimensional fan-out type integrated packaging structure. By adoption of the design scheme of the invention, passive devices and bare wafers of different dimensions can be integrated and packaged synchronously, so that the degree of integration is greatly improved, and the integrated packaging structure is particularly suitable for applications adopting a large number of passive devices, such as wifi, PA, PMU and the like; and meanwhile, by virtue of the three-dimensional stacking mode, the packaging area is greatly reduced.