129results about How to "Save pins" patented technology

The invention relates to a control circuit and a control method of a flyback convertor and an alternating current-direct current power converting circuit applying the control circuit of the flyback convertor. Within each switch period, an opening signal generating circuit is used for receiving drain-source voltage of a power switch in the flyback converter; when the drain-source voltage reaches valley value, opening signal is generated to control the turn-on of the power switch; a turn-off signal generating circuit is used for generating a turn-off signal after the power switch turns on and a turn-on time interval is completed according to a feedback error signal of a received output electric signal for representing the flyback converter; and the turn-off signal controls the power switch to turn off, so as to lead input current and input voltage of the flyback converter in a same phase and keep the output electric signal of the flyback converter constant.

The invention discloses a flexible resistive-type pressure sensor array and a preparation method therefor. The flexible resistive-type pressure sensor array comprises a surface packaging layer, an electrode layer and a functional layer, wherein the electrode layer comprises a base film and a plurality of thin film metal wires arranged on the base film at equal intervals. The thin film metal wiresare connected with a multi-way gate. The functional layer is a flexible elastic film with a convex microstructure on the surface, and the flexible elastic film is covered by a plurality of conductivemetal wires arranged at equal intervals, wherein the conductive metal wires are connected with an operational amplifier. The thin film metal wires of the electrode layer and the conductive metal wiresof the functional layer are stacked and assembled in a vertical crossing manner. The pressure sensor array provided by the invention has a series of advantages, such as high sensitivity, fast response and recovery, low operating voltage, large array scale, simple preparation process, and low cost.

An integrated circuit for providing programmable microphone interface includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. In an embodiment, the integrated circuit includes a bias circuit, an amplifier circuit and two feedback circuits. The amplifier circuit includes a first input, a second input, and an output. The first input receives either the input signal or a feedback signal, depending upon mode control signals. The second input receives either the feedback signal or the input signal depending upon the mode control signals. The first feedback circuit is in communication with the output and the first input of the amplifier and includes a first resistor and a first capacitor connected in parallel. The second feedback circuit includes an integrator circuit and provides the feedback signal. The mode control signals can be set in a programmable mode control register.

An integrated circuit for providing programmable microphone interface includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. The integrated circuit includes a bias circuit, an amplifier circuit, and two feedback circuits. The bias circuit provides a microphone bias signal to the microphone and provides a sensed microphone signal. The amplifier circuit includes a first input, a second input, and an output. The first input is configured to receive the sensed microphone signal, a first feedback signal, and a second feedback signal. The second input is configured to receive a first reference signal. The feedback circuits are in communication with the output and the first input of the amplifier circuit. In a specific embodiment, the first feedback circuit includes an RC circuit and the second feedback circuit includes an integrator.

The invention provides a chip provided with a multiplex pin. The chip comprises the multiplex pin. When the multiplex pin is applied to another pin besides a test pin, voltage of the multiplex pin is larger than first threshold voltage or smaller than second threshold voltage. When the voltage of the multiplex pin is smaller than the first threshold voltage and larger than the second threshold voltage, the chip is in a test mode, and at the moment, the multiplex pin serves as the test pin and the first threshold voltage is larger than the second threshold voltage. Compared with the prior art, the chip is provided with the multiplex pin, whether the multiplex pin serves as the test pin is confirmed through testing of the voltage of the multiplex pin. The multiplex pin can serve as other pins, so the number of pins of the chip is reduced and a packaging area is reduced.

The embodiment of the invention discloses a method, a device and a chip for reading a boot loader based on a system on chip (SoC). A nonvolatile memory and a read-only memory (ROM) are arranged on the SoC, and the method comprises the following steps of: after the SoC is electrified, acquiring a control bit saved on the nonvolatile memory; and reading the boot loader from a memory indicated by the acquired control bit. The memory for reading the boot loader is indicated by the control bit saved on the nonvolatile memory of the SoC, so that a pin on the SoC is saved; and moreover, because the control bit saved on the nonvolatile memory is difficult to change, the boot loader on the memory is difficult to read by maliciously changing the control bit correspondingly; and therefore, the safety of the memory is improved.

The invention relates to the technical field of electronics and discloses a prompt circuit and electronic equipment. The prompt circuit is applied to the electronic equipment; a control unit controlsa first output end to output high level and a prompt unit begins to work when a power management chip determines that a VBUS pin of a USB interface outputs charging voltage and a first detection terminal of the control unit detects successful handshake of an external charger and the USB interface based on a charging protocol; and the control unit controls a second output end to output high level and the prompt unit stops working when a second detection terminal of the control unit detects that a battery is full of electricity. According to the prompt circuit and the electronic equipment provided by the embodiment of the invention, an accurate charging prompt can be made according to the actual charging condition, the problem of false charging or the problem that the charging prompt cannotbe made is effectively solved and the cost is reduced.

The invention provides a display device, a display panel and a detection method thereof, and relates to the technical field of display. The display panel comprises a display module, the display moduleis provided with a display area and a peripheral area surrounding the display area, the display area is provided with sub-pixels capable of being closed in response to detection signals, and the sub-pixels comprise the first sub-pixels and the second sub-pixels; The peripheral area comprises a first area, a second area and a third area, and the first area comprises a wiring area and a binding area. A first detection line comprises a first section, a second section and a first bent section, the first section and the second section are arranged in the wiring area, and the first bent section extends into the second area; the second detection line comprises a third section, a fourth section and a second bent section, the third section and the fourth section are arranged in the wiring area, the second bent section extends into the third area, and the second section is connected with the third section through a connecting line; a first switching element is connected with the second sectionand the first sub-pixel and is used for responding to the control signal to be conducted; and a second switching element is connected with the fourth section and the second sub-pixel and is used for responding to the control signal to be conducted.

The invention relates to an embedded self-capacitance touch liquid crystal display device and a data processor and a screen body thereof. The embedded self-capacitance touch liquid crystal display device comprises reuse electrodes, touch controlled switch devices and data processing chips. The touch controlled switch devices are divided into N touch sets. When the data processing chips are used for conducting touch detection and controlling, and after touch controlled ends of the touch controlled switch devices of all touch sets receive connected touch control signals according to touch time slices, all reuse electrodes in the same touch set are electrically connected with a touch module in one touch time slice. Through the scheme of electrode reuse and pin reuse, the pins of the data processing chips of the embedded self-capacitance touch liquid crystal display device are reduced, then the number of the contact bump of a touch detection channel is reduced, the area of the chips is reduced, and the boundary range of a touch display panel is reduced.

The invention discloses an active noise reduction controller which comprises a substrate, a silicon microphone, an ASIC chip integrated through an ASIC technology, and a shell. The silicon microphone and the ASIC chip are fixed to the substrate and disposed in a closed space formed by the shell and the substrate, the silicon microphone and the ASIC chip are connected in a pressure welding manner through a first group of gold wires, and the ASIC chip and the substrate are connected in a pressure welding manner through a second group of gold wires. The substrate or the shell is provided with a sound hole in a position corresponding to the silicon microphone. The substrate is further provided with a lead bonding pad comprising an earphone unit positive end bonding pad, an earphone unit negative end bonding pad, a power input end bonding pad, an audio input end bonding pad and a common grounding end bonding pad, and the lead bonding pad is connected with the second group of gold wires through a printed circuit on the substrate.

The invention provides a built-in self-test circuit, a built-in self-test system and a built-in self-test method for a flash memory. The built-in self-test circuit comprises a self-reading test module, a self-erasing test module, a self-programming test module and a command conversion module, wherein the self-reading test module is used for testing reading operation of the flash memory and sending a reading test result to the command conversion module, the self-erasing test module is used for testing erasing operation of the flash memory and sending an erasing test result to the command conversion module, the self-programming test module is used for testing programming operation of the flash memory and sending a programming test result to the command conversion module, and the command conversion module is used for sending test commands inputted by a test machine to the self-reading test module, the self-erasing test module and the self-programming test module, and sending the reading test result, the erasing test result and the programming test result to the test machine.

A method for testing a high-pass test chip of the single-cell travelling wave dielectric spectrum comprises the following procedures: respectively connecting each terminal of the test chip to the source end of the sinusoidal voltage signal which has same frequency to lead to that the advance mount or hysteresis amount of the phase between random two adjacent electrodes is equal, dripping the liquid sample containing the cell to be tested into the inner part of the test chip from the injection port (06), then projecting light pattern to the cell initial collection area (32) at the central areaof the electrode group (10), projecting a plurality of strip light patterns (31) with width about the cell diameter from the lower part of the chip substrate (01) to the microelectrode group (10) to form a virtual electrode array, regulating the frequency of a waveform generator, and at the same time recording the horizontal moving image of all cells in the frequency band through a CCD and an image recorder on a microscope. If the cell number of the completed test actually has already satisfied the requirement of the test, then the test procedure ends.

The invention provides a driving device compatible with various display protocol hardware interfaces. A driving circuit comprises a protocol compatible physical layer compatible with various display protocols, a plurality of GPIO interfaces and a plurality of data channels. Wherein the protocol compatible physical layer is provided with a multi-path signal input end and a multi-path signal outputend; the protocol compatible physical layer is used for being compatible with hardware interfaces of a plurality of display protocols, the input end of the protocol compatible physical layer is connected with the output ends of the hardware interfaces of different display protocols, and the output end of the protocol compatible physical layer is connected with one or more input end Pad windows ofthe GPIO interfaces; Wherein the input end Pad window of one or more of the GPIO interfaces is connected with the output end of the protocol compatible physical layer, and the output end of one or more of the GPIO interfaces is connected with the display module; Wherein the plurality of data channels are formed by a protocol compatible physical layer, a plurality of GPIO interfaces, a plurality ofGPIO interfaces and a display module.

The invention discloses a load current detection circuit and method for a switching power supply converter. Only a switching tube peak current sampling circuit, a sampling hold circuit, an inductive current compensation circuit and a low-pass filter circuit need to be arranged; the method comprises the following steps: sampling to obtain a peak current of the Boost type or Buck-Boost type switching power supply converter in an inductive current rising period, namely a switching tube conduction period, in a current switching period; sampling and holding a peak current sampling value of an inductive current rising period, namely a switching tube conduction period, through a sampling and holding circuit; and in the conduction period of the follow current tube, compensating the peak current sampling value in the conduction period of the switching tube through the inductive current compensation circuit, outputting the compensated inductive current signal to the low-pass filter after being maintained by the sample hold circuit, and acquiring the load current signal of the switching power supply converter after being smoothed by the low-pass filter. The circuit is simplified, the detection accuracy and reliability are improved, and the cost and power consumption are reduced.

A control system using internal integrated circuit bus transmission to control signal is prepared as setting multiple pin on controller, connecting these pins separately to clock line and multiple data line one by one, providing relevant clock signal and control signal to each controlled peripheral unit with the same address by said controller through each data line and clock line.

An integrated circuit for providing programmable microphone interface includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. The integrated circuit includes a bias circuit, an amplifier circuit, and two feedback circuits. The bias circuit provides a microphone bias signal to the microphone and provides a sensed microphone signal. The amplifier circuit includes a first input, a second input, and an output. The first input is configured to receive the sensed microphone signal, a first feedback signal, and a second feedback signal. The second input is configured to receive a first reference signal. The feedback circuits are in communication with the output and the first input of the amplifier circuit. In a specific embodiment, the first feedback circuit includes an RC circuit and the second feedback circuit includes an integrator.

The invention provides an improved audio circuit. The improved audio circuit comprises a microphone bias circuit, a microphone circuit, a sensing resistor, a programmable gain amplifier, an analog to digital converter, a filtering module and a digital signal processor, wherein the microphone bias circuit is used for providing a bias voltage; the microphone circuit is used for receiving an audio signal, generating a current signal reflecting the audio signal, and outputting the current signal reflecting the audio signal through an output end of the microphone circuit; the sensing resistor is connected between the bias voltage and the output end of the microphone circuit; a first input end of the programmable gain amplifier is connected with one end of the sensing resistor; a second input end of the programmable gain amplifier is connected with the other end of the sensing resistor; an input end of the analog to digital converter is connected with an output end of the programmable gain amplifier; an input end of the filtering module is connected with the output end of the programmable gain amplifier; and an input end of the digital signal processor is connected with an input end of a filter. The audio circuit can be subjected to high-pass filtering in a digital part without arrangement of any external stopping condenser, so that pins of chips can be reduced, and the cost is lowered.

The message storing method for wide-band digital communication chip includes the following steps: defining the width of logic address and the physical address, with the logic address being one bit wider than the physical address; sectioning the memory region of the physical address in 2048 bytes each and addressing in the basic address plus offset, with the addressing space of the offset being within 1536 bytes; setting the lower 1536 bytes of each sections as message storing area and the rest 512 bytes as extended memory area; defining the MSB 0 / 1 as logic address addressing range of corresponding message storing area and MSB 1 / 0 as logic address addressing range of corresponding extended memory area; and establishing the mapping mechanism between the logic address and the physical address to realize the continuity of memory units, basic addresses and offset of the extended memory area addresses. The present invention raises the utilization of the memory space.

The invention discloses a lightning protection device comprising a piezoresistor and a gas discharge tube, the piezoresistor is provided with a first surface and a second surface opposite to the firstsurface, and a first electrode connected with the piezoresistor is welded on the first surface of the piezoresistor, and a second electrode connected with the piezoresistor is welded on the second surface of the piezoresistor, one side face of the gas discharge tube is welded on the second surface of the piezoresistor and is connected with the second electrode, and a third electrode connected with the gas discharge tube is welded on the other side face of the gas discharge tube. The invention further discloses a surge protection device comprising the lightning protection device. Due to the direct welding of the lightning protection device with the gas discharge tube through the piezoresistor, the welding pins and welding points are reduced, the circuit loop is shorter, and meanwhile, theresidual voltage of the whole lightning protection device circuit can be lower, and the corresponding time is shorter.

The invention discloses a Profinet communication protocol conversion card and a conversion method. The Profinet communication protocol conversion card comprises an MCU, a CPLD chip and a TPS-1 protocol chip, wherein the MCU is respectively connected to the CPLD chip and the TPS-1 protocol chip; the MCU is used for reading a control instruction of a Profinet master station through the TPS-1 protocol chip and writing data into a frequency converter through the CPLD chip after protocol data processing, and acquiring state data of the frequency converter through the CPLD chip, writing the state data into the TPS-1 protocol chip after protocol data processing and sending the state data to the Profinet master station in order to realize data exchange. The Profinet communication protocol conversion card supports a 8 / 16-bit parallel bus and is compatible with a hardware interface of an existing 8-bit bus, the software development is easy to realize, the number of chip pins is small, the designis simple, and the development period is short.

The application discloses a display panel, a pixel circuit and a driving method thereof. The pixel circuit includes a driving chip, and a plurality of pixel circuit units and a plurality of detectingcircuit units connected to the driving chip; the pixel circuit unit includes a first switching transistor and an electroluminescent element; each detecting circuit unit includes a selection circuit, and the selection circuit includes a second switching transistor and a connection switching transistor; a first access end of the second switching transistor is connected to an anode of the electroluminescent element in the pixel circuit unit through the connection switching transistor and the pixel circuit unit; the control end of the second switching transistor is connected to a first timing signal end; the second access end of the second switching transistor is connected to the driving chip; and at least two adjacent detecting circuit units are connected in a second direction through connection terminals, and the two adjacent detecting circuit units are connected to the same pin of the driving chip through the connection terminals. The application can facilitate the anode potential detection of a high pixel density display panel, and can improve the display effect of the display panel.

The invention discloses an FPGA chip and an FPGA system and belongs to the field of electrical apparatus elements. A bypass control circuit is integrated with an FPGA chip and is connected with another FPGA chip, so that the regulation of FPGA system layout can be simply and quickly achieved, and the usage amount of pins for the FPGA chips is also reduced. An FPGA chip is characterized in that a bypass controller and a bypass control circuit are arranged in the FPGA chip, wherein the bypass control circuit is connected with the bypass controller; in an FPGA system on which the FPGA chip is arranged, the bypass control circuit is connected with multiple digital signal processors; the bypass control circuit is used for carrying out data bypassing on the digital signal processors according to a bypassing instruction descended by the bypass controller.

The invention discloses a power tube overload detection circuit of a switching power supply. The overload detection circuit comprises a logic driving circuit, wherein an output end of the logic driving circuit is connected with a control end of a power NMOS (N-channel Metal Oxide Semiconductor) tube; the logic driving circuit comprises a PWM (Pulse-Width Modulation) signal generator, and a first PMOS (P-channel Metal Oxide Semiconductor) tube and a first NMOS tube which are used for directly driving a power NMOS gate electrode and form a phase inverter connection type; drain ends of the first PMOS tube and the first NMOS tube serve as the output end of the logic driving circuit; and the output end of the logic driving circuit is connected with a pull-down branch circuit. With the adoption of the power tube overload detection circuit of the switching power supply, inductive current zero passage and resonance wave trough detection can be achieved by control and detection on a gate electrode signal, multiple peripheral cells are saved, pins of a chip are reduced, and the cost of the chip and a power supply system is lowered greatly.

The invention relates to a status switching circuit of an LED controller. The status switching circuit of the LED controller comprises a DC power supply and a switch thereof which are correspondingly connected with an LED controller power supply input terminal and a power supply ground input terminal, and also comprises a capacitor which is bridged on the power supply and the power supply ground input terminal. The LED controller detects the voltage of the power supply input terminal to switch status so as to integrate the LED controller detection input terminal with the power supply input terminal; and a pin of the LED controller is reduced so that the cost of the circuit is reduced and the circuit layout is convenient.

The invention discloses a jitter frequency control circuit which comprises a detection module and an enabling module. The jitter frequency control circuit decides whether to be added with a jitter frequency function by detecting a pin state. Correspondingly, the invention further discloses a jitter frequency control method. The control circuit disclosed by the invention is simple in structure, convenient to use and high in integration; and an application engineer can select whether to adopt the jitter frequency function only by increasing or decreasing one peripheral component (such as a capacitor), so that the design difficulty of the application engineer is reduced, and design steps are simplified.

An embodiment of the invention provides sending and receiving apparatuses with chips interconnection and sending and receiving methods and systems, which relate to the technical field of integrated circuits, wherein the sending apparatus comprises a serial data conversion circuit and at least a sending pin; an input end of the serial data conversion circuit is connected to a data sending processor; an output end of the serial data conversion circuit is connected to at least the sending pin; the serial data conversion circuit is used for obtaining n bit serial data from the data sending processor according to the vld / rdy handshake protocol; the n bit serial data is converted into a m bit transmission data; then according to the vld / rdy handshake protocol, the m bit transmission data is sent to the receiving apparatus with chips interconnection through m sending pins; n is an integer greater than 1; and m is an integer greater than 0 less than 1. The invention is suitable for the scene of data transmission.

The invention discloses a method for controlling a drive circuit of a cold-cathode fluorescence lamp (CCFL), comprising the following steps: sampling a current or voltage signal of the CCFL to generate a feedback signal; detecting the state of the lamp to generate a state signal; processing the state signal and the feedback signal to generate a control signal; comparing the control signal with a frequency sweeping threshold signal to generate a comparison signal; and based on the comparison signal, using the control signal to selectively adjust the duty cycle of a switching control signal output by the drive circuit or control the frequency of the switching control signal output by the drive circuit to be swept highly. The invention also discloses a control circuit for realizing the method. The invention realizes adjusting the duty cycle of the switch of the drive circuit of the CCFL and controlling the frequency of the switch to be swept highly only via a control signal, thus simplifying circuit design and lowering the cost.