Sending and receiving apparatuses with chip interconnection and sending and receiving method and system

Abstract

An embodiment of the invention provides sending and receiving apparatuses with chips interconnection and sending and receiving methods and systems, which relate to the technical field of integrated circuits, wherein the sending apparatus comprises a serial data conversion circuit and at least a sending pin; an input end of the serial data conversion circuit is connected to a data sending processor; an output end of the serial data conversion circuit is connected to at least the sending pin; the serial data conversion circuit is used for obtaining n bit serial data from the data sending processor according to the vld / rdy handshake protocol; the n bit serial data is converted into a m bit transmission data; then according to the vld / rdy handshake protocol, the m bit transmission data is sent to the receiving apparatus with chips interconnection through m sending pins; n is an integer greater than 1; and m is an integer greater than 0 less than 1. The invention is suitable for the scene of data transmission.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, in particular to an inter-chip interconnection sending and receiving device, sending and receiving method and system. Background technique [0002] After the semiconductor industry enters the era of ultra-deep submicron and even nanometer processing, a complex electronic system can be realized on a single integrated circuit chip, such as mobile phone chips, digital TV chips, etc. With the advancement of technology, more functions are expected to be realized on a single chip. SOC (System On Chip, System on a Chip) technology is produced under the general direction of the transformation from Integrated Circuit (IC) to Integrated System (IS). With the development of semiconductor process technology, IC designers can Integrating increasingly complex functions onto a single silicon chip. Because SOC can make full use of the existing design accumulation, it has significantly impro...

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Problems solved by technology

[0005] There are at least the following problems in the prior art: if the SOC function verification is carried out through the direct interconnection of at least two FPGAs, when the bits of the interactive signals are more, more pins need to be occupied. At this time, at least two FPGAs The wiring of the signal lines connected between them is also relatively complicated, which increases the complexity of the interconnection between FPGAs.

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