Three-dimensional multi-chip encapsulation module based on buried substrate and method

Abstract

The invention provides a buried substrate based multi-chip module structure for realizing three-dimensional high-density encapsulation (3D-MCM). The upper surface and the lower surface of the substrate have concave cavity structures; different chips having larger size difference are placed and wires are arranged in the cavity structures having different sizes so as to form a buried three-dimensional encapsulation structure; a plurality of chips are interconnected by using a conventional wire bonding method; a chip protection mode adopts two packing processes, namely sealing glue dropping and surrounding dam packing; a pin output form adopts a peripheral ball grid array mode; and by the concave cavity structures, the encapsulation area is reduced, the encapsulation density is enhanced, the bonded wire is shortened effectively, and the signal delay is decreased. The whole process and the surface assembling process are compatible with each other and have characteristics of simpleness and low cost. By the concave cavity structures on the upper surface and the lower surface of the substrate, the warping of the substrate is decreased and the reliability of the three-dimensional encapsulation structure is improved.

Description

technical field [0001] The invention relates to a structure and method of three-dimensional multi-chip packaging realized by using an embedded substrate. More precisely, the invention relates to a multi-chip module structure and method based on an H-shaped embedded substrate to realize three-dimensional packaging, which belongs to microelectronics packaging field. Background technique [0002] Multi-chip module (MCM) packaging is to package multiple chips on a substrate to complete certain circuit functions. On the basis of multi-chip module XY two-dimensional packaging, a three-dimensional multi-chip module (3D-MCM) has emerged in the Z direction. It stacks chips together along the Z axis to maximize packaging density and reduce package size. Three-dimensional packaging has the advantages of small size and volume, higher assembly efficiency, further shortened delay, further reduced noise, reduced power consumption, faster speed, and increased bandwidth. [0003] There ar...

AI Technical Summary

Problems solved by technology

It is not suitable for the package of two bare chips with wire bonding interconnection.

In addition, the existence of the concave cavity on the lower surface of the Π-shaped substrate will cause the asymmetry of the mirror surface of the substrate structure, and aggravate the thermal expansion and contraction mismatch between the upper and lower layers of the substrate, which will easily cause the warping problem of the substrate

This will pose a potential hazard to the thermal-mechanical reliability of large-scale chips

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