Method of forming a wafer backside interconnecting wire

Abstract

A method of forming a wafer backside interconnecting wire includes forming a mask layer on the back surface, the mask layer including at least an opening corresponding to the bonding pad, performing a first etching process from the back surface to remove the wafer unprotected by the mask layer to form a recess, removing the mask layer, and forming an interconnecting wire on the back surface.

Description

BACKGROUND OF INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a method of forming a wafer backside interconnecting wire, and more particularly, to a method of forming a wafer level chip scale package (WLCSP) using the wafer backside interconnecting wire. [0003] 2. Description of the Prior Art [0004] The package technologies of integrated circuits are substantially classified into two types: pin through hole (PTH) and surface mounting technology (SMT). Currently, the ball grid array (BGA) package is the most popular SMT type package. Please refer to FIG. 1, which is a schematic diagram of a BGA package 10. As shown in FIG. 1, the BGA package 10 includes a substrate 12, a die 14 bonded to the surface of the substrate 12 with silver glue 16, and a cap layer 18 which covers the die 14 and the surface of the substrate 12. The die 14 includes a circuit layout (not shown) and a plurality of metal bonding pads 20 electrically connected to the circuit layou...

AI Technical Summary

Benefits of technology

[0011] The method according to the present invention is characterized by forming the interconnecting wires on the backside of the wafer, and thus the area of the package is effectively reduced. In addition, since the wafer is diced subsequent to packaging, the method benefits from mass production, low cost and consistency with standard semiconductor processes.

Problems solved by technology

However, this leads to some problems such as the warpage of the substrate 12.

However, the CSP formed by any of the aforementioned technologies still has some disadvantages or limitations.

Regarding the FP BGA technology, although an FP BGA package is consistent with the CSP definition, the FP BGA package suffers from the stress problem between the die and the substrate.

In addition, the gap of two adjacent solder balls is limited, and an excessively small gap causes problems while welding the substrate and the PCB.

Furthermore, if the die and the substrate are packaged by wire bonding, the area of the package cannot be further reduced.

Regarding the FC technology, although the area of an FC package is smaller, the FC technologies cannot be applied to forming some devices, such as optical sensor devices, and print head devices.

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