Multi-substrate region-based package and method for fabricating the same

Abstract

A multi-substrate region-based package and a method for fabricating the same are provided. An active surface of a chip is divided into a plurality of functional regions, and each of the functional regions is electrically connected to a corresponding substrate via bonding wires. Each of the functional regions has a separate system, and the circuit layout thereof is not limited by the substrate or other systems but can be flexibly and independently designed, thereby allowing the package to be made smaller and thinner. Each set of the functional region and its corresponding substrate functions as an independent unit, such that the substrates are not affected by each other, thereby providing good compatibility, improved reliability and reduced packaging area.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to semiconductor packages, and more particularly, to a multi-substrate region-based package and a method for fabricating the same.[0003]2. Description of Related Art[0004]Conventional leadframe-based semiconductor package, such as a quad flat package (QFP), is fabricated by preparing a leadframe comprising a die pad and a plurality of leads, mounting a chip on the die pad, forming a plurality of bonding wires for electrically connecting bond pads formed on the chip to the corresponding leads, and encapsulating the chip and the bonding wires by an encapsulant.[0005]Such conventional leadframe-based semiconductor package however has a drawback that the leads serving as input / output (I / O) connections can only be disposed around the encapsulant, that is, the number of I / O connections provided is limited by the size of the encapsulant, thereby failing to fulfill the requirement of further increa...

AI Technical Summary

Benefits of technology

The present invention provides a multi-substrate region-based package and a method for fabricating the same using HDP technologies. The package includes a chip with a plurality of functional regions, each having a first electrical connecting portion, and a substrate with a second electrical connecting portion connected to the first electrical connecting portion of the chip through bonding wires. The substrate also has a plurality of bond pads formed on its surface. The package provides good compatibility, reduced packaging area, improved reliability, and reduced heat dissipation. The method allows for system integration and circuitry design on each of the functional regions, resulting in a smaller and thinner package. The chip is divided into a plurality of functional regions each being mounted with a corresponding substrate to prevent damage to the bonding wires. The technical effects of the present invention include increased yield, improved reliability, reduced packaging area, and enhanced heat dissipation.

Problems solved by technology

Such conventional leadframe-based semiconductor package however has a drawback that the leads serving as input / output (I / O) connections can only be disposed around the encapsulant, that is, the number of I / O connections provided is limited by the size of the encapsulant, thereby failing to fulfill the requirement of further increase in I / O connections for the electronic products nowadays.

However, the conventional BGA package configuration has gone out of date due to its poor compatibility with the progress trends of having lower profile, more functions and shorter life span for the electronic products.

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