Multi-substrate region-based package and method for fabricating the same

Abstract

A multi-substrate region-based package and a method for fabricating the same are provided. An active surface of a chip is divided into a plurality of functional regions, and each of the functional regions is electrically connected to a corresponding substrate via bonding wires. Each of the functional regions has a separate system, and the circuit layout thereof is not limited by the substrate or other systems but can be flexibly and independently designed, thereby allowing the package to be made smaller and thinner. Each set of the functional region and its corresponding substrate functions as an independent unit, such that the substrates are not affected by each other, thereby providing good compatibility, improved reliability and reduced packaging area.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to semiconductor packages, and more particularly, to a multi-substrate region-based package and a method for fabricating the same.[0003]2. Description of Related Art[0004]Conventional leadframe-based semiconductor package, such as a quad flat package (QFP), is fabricated by preparing a leadframe comprising a die pad and a plurality of leads, mounting a chip on the die pad, forming a plurality of bonding wires for electrically connecting bond pads formed on the chip to the corresponding leads, and encapsulating the chip and the bonding wires by an encapsulant.[0005]Such conventional leadframe-based semiconductor package however has a drawback that the leads serving as input / output (I / O) connections can only be disposed around the encapsulant, that is, the number of I / O connections provided is limited by the size of the encapsulant, thereby failing to fulfill the requirement of further increa...

AI Technical Summary

Benefits of technology

[0014]Still another objective of the present invention is to provide a multi-substrate region-based package and a method for fabricating the same, which are cost-effective, increase yield and avoid complex packaging.

[0015]A further objective of the present invention is to provide a multi-substrate region-based package and a method for fabricating the same, which provide good compatibility.

[0016]A further objective of the present invention is to provide a multi-substrate region-based package and a method for fabricating the same, which provide a small packaging area, high heat dissipation and good reliability.

[0022]Therefore, the multi-substrate region-based package and the method for fabricating the same in the present invention use the HDP technologies to form a plurality of functional regions on the active surface of the chip. Each of the functional regions has a first electrical connecting portion and a substrate electrically connected the first electrical connecting portion. The integration of the plurality of functional regions in a single chip may increase yield while avoiding the use of the conventional complex SiP packaging technology. In addition, by combining a plurality of substrates with different functional regions of the chip, good compatibility, improved reliability and reduced packaging area can be provided. Moreover, the non-active surface of the chip is exposed, such that heat dissipation of the package can be greatly enhanced.

[0023]Furthermore, in the present invention, the chip is divided into a plurality of functional regions each being mounted with a corresponding substrate, such that system integration and circuitry design can be performed on each of the functional regions respectively, thereby allowing the package to be designed or made smaller and thinner as desired. This arrangement can also prevent bonding wires from being torn or pulled on each of the functional regions when the functional region is subjected to thermal expansion, thereby maintaining integrity of the bonding wires.

Problems solved by technology

Such conventional leadframe-based semiconductor package however has a drawback that the leads serving as input / output (I / O) connections can only be disposed around the encapsulant, that is, the number of I / O connections provided is limited by the size of the encapsulant, thereby failing to fulfill the requirement of further increase in I / O connections for the electronic products nowadays.

However, the conventional BGA package configuration has gone out of date due to its poor compatibility with the progress trends of having lower profile, more functions and shorter life span for the electronic products.

Images