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Apparatus for variable word length computing in an array processor

an array processor and variable word technology, applied in the direction of program control, multi-processor architecture, instruments, etc., can solve the problems of complex design of modern microprocessors, one task, and tasks to which they are not well suited, so as to achieve dynamically alter the effect of effective arrangement of processing elements

Inactive Publication Date: 2004-12-16
MTEKVISION CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

0017] Another aspect of the invention provides a circuit and architecture of processing elements such that the effective arrangement of

Problems solved by technology

Designing a modern microprocessor is a complex task that demands careful balance between cycle times, instruction set architecture, instruction latency, otherwise known as cycle-per-instruction, and finally die area costs.
While the above developments have provided considerable increases in the performance of "serial" microprocessors there are tasks to which they are not well suited.
One task to which serial processors are not well suited is the manipulation of multi-media data.
One of the major shortcomings with such an approach is the fact that for certain types of processing, namely, multimedia applications, very wide data paths are very often unutilized.
However, historically these processing architectures have encountered problems including high power consumption.
This high power consumption is mainly a result of the line resistance associated with the large number of interconnects associated with an array of SIMD processors.
The resistance associated with this power consumption also reduces the speed of communications.
The arrangement taught in the above patent greatly reduces resistance and delay issues.
Further the arrangement taught in the '274 patent reduces timing problems that are a result of uneven interconnect line length.
However, bit serial processing introduces its own processing problems including: realignment of the data for bit-serial processing (commonly referred to as corner-turning), non-uniform cycle execution time, and increased instruction latency.
Another approach for converging on optimal architecture is limiting the scope of applications, reducing the flexibility of such processor.
This requirement once again forces the processing to be limited by the throughput of the processing element.

Method used

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  • Apparatus for variable word length computing in an array processor
  • Apparatus for variable word length computing in an array processor
  • Apparatus for variable word length computing in an array processor

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Embodiment Construction

[0027] FIG. 1 shows a data processor according to an embodiment of the present invention. The data processor 1 comprises a computational unit 3 having a plurality of SIMD based processing elements 5, 7, 9, 11, each of which has access to a memory 13. Each processor element 5, 7, 9, 11 has an arithmetic logic unit (ALU) 15, 17, 19, 21 each having an input port 23 and an output port 25. The input port 23 of each ALU is directly coupled to the output port of the neighboring ALU to its right to enable data (e.g. a bit) to propagate from the output 25 to the input 23 of adjacent ALUs. Each processor element further comprises one or more registers 27 and a multiplexer 29 for switchably coupling one or more of a plurality of inputs to a register. In this embodiment, inputs to the multiplexer include the output from its local ALU, the outputs from its neighboring ALUs to its left and right, and an output from the memory 13.

[0028] The data processor 1 has a control circuit 31 (which is also ...

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PUM

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Abstract

A computational unit comprises a processor having a plurality of processing elements, each having an arithmetic logic unit, and a controller for controlling the processor elements. The processor can provide a respectivef bit of a multiple bit word to each of the processor elements and enables signals to be transmitted between the arithmetic logic units to enable the units to perform a parallel operation on the bits of the multiple bit word. Extension circuitry is provided for selectively coupling one or more computational units together to combine their parallel processing capability.

Description

[0001] The invention generally relates to a processing apparatus and more particularly relates to a processing apparatus that contains a number of processing units capable of operating in parallel.[0002] Designing a modern microprocessor is a complex task that demands careful balance between cycle times, instruction set architecture, instruction latency, otherwise known as cycle-per-instruction, and finally die area costs. Many traditional microprocessors are designed to execute a single instruction at a time. The processor executes instructions in a serial fashion. This paradigm generally implies a single processing core. The performance of such microprocessors has been improved by two basic approaches. The first of these is the data path width. Over time the data path width has increased from the conceptual 1-bit Turing Machine, to some of the latest 128-bit processors. Second, the performance of the processor has also been improved by increasing the rate at which instructions are...

Claims

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Application Information

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IPC IPC(8): G06F3/00G06F7/575G06F9/302G06F13/16G06F15/173G06F15/80
CPCG06F7/575G06F13/1663G06F15/17337G06F15/17375G06F15/8015G06F2207/382G06F2207/3828G06F9/30036
Inventor GIERNALCZYK, ERICSTEWART, MALCOLM
Owner MTEKVISION CO LTD
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