Apparatus for variable word length computing in an array processor

Abstract

A computational unit comprises a processor having a plurality of processing elements, each having an arithmetic logic unit, and a controller for controlling the processor elements. The processor can provide a respectivef bit of a multiple bit word to each of the processor elements and enables signals to be transmitted between the arithmetic logic units to enable the units to perform a parallel operation on the bits of the multiple bit word. Extension circuitry is provided for selectively coupling one or more computational units together to combine their parallel processing capability.

Description

[0001] The invention generally relates to a processing apparatus and more particularly relates to a processing apparatus that contains a number of processing units capable of operating in parallel.[0002] Designing a modern microprocessor is a complex task that demands careful balance between cycle times, instruction set architecture, instruction latency, otherwise known as cycle-per-instruction, and finally die area costs. Many traditional microprocessors are designed to execute a single instruction at a time. The processor executes instructions in a serial fashion. This paradigm generally implies a single processing core. The performance of such microprocessors has been improved by two basic approaches. The first of these is the data path width. Over time the data path width has increased from the conceptual 1-bit Turing Machine, to some of the latest 128-bit processors. Second, the performance of the processor has also been improved by increasing the rate at which instructions are...

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Benefits of technology

0017] Another aspect of the invention provides a circuit and architecture of processing elements such that the effective arrangement of

Problems solved by technology

Designing a modern microprocessor is a complex task that demands careful balance between cycle times, instruction set architecture, instruction latency, otherwise known as cycle-per-instruction, and finally die area costs.

While the above developments have provided considerable increases in the performance of "serial" microprocessors there are tasks to which they are not well suited.

One task to which serial processors are not well suited is the manipulation of multi-media data.

One of the major shortcomings with such an approach is the fact that for certain types of processing, namely, multimedia applications, very wide data paths are very often unutilized.

However, historically these processing architectures have encountered problems including high power consumption.

This high power consumption is mainly a result of the line resistance associated with the la

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