Methods and systems for DSP-based receivers

a receiver and digital signal technology, applied in the field of receivers, can solve the problems of limited adc speed, limited digital signal processing speed, and difficult design of adc, and achieve the effect of high data rate multi-path dsps and high speed multi-paths

Inactive Publication Date: 2007-07-17
AVAGO TECH INT SALES PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In many applications, the ADC is challenging to design.
Conventional communications systems have limited ADC speeds and limited digital signal processing speeds.

Method used

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  • Methods and systems for DSP-based receivers
  • Methods and systems for DSP-based receivers
  • Methods and systems for DSP-based receivers

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Table Of Contents

I. Introduction

[0054]A. Receivers and Transceivers

[0055]B. Equalization

II. High Speed, DSP-Based Receiver

[0056]A. Parallel ADC and DSP

III. Design and Control Considerations

[0057]A. Path-Based Timing Recovery and Phase Error Compensation[0058]1. Decision-Directed Timing Recovery[0059]2. Phase Selector[0060]a. DAC-Based Phase Selector[0061]b. Resistive Interpolation Ring

[0062]B. Gain and Offset Mismatch Compensation[0063]1. DSP-Based Adaptive Path Gain and Offset Mismatch Control[0064]2. Automatic Gain Control (AGC)[0065]3. Analog Compensation[0066]4. Alternative Implementations

IV. Parallel Equalization

[0067]A. Parallelization of a Viterbi Decoder

V. Error Correction

VI. Methods of Operation

VII. Conclusions

I. Introduction

[0068]A. Receivers and Transceivers

[0069]The present invention is directed to receivers and, more particularly, to digital signal processing (“DSP”) based receivers, multi-channel receivers, timing recovery schemes, and equalization schemes. Various fea...

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Abstract

Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and / or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority to U.S. Provisional Application No. 60,273,215, filed Mar. 1, 2001, titled “High-Speed Analog to Digital Conversion System for Communications Applications,” incorporated herein by reference in its entirety. The application is a Continuation-In-Part of U.S. patent application Ser. No. 09 / 909,896, titled “Methods and Systems for Digitally Processing Optical Data Signals, which claims priority to U.S. Provisional Application No. 60 / 219,918, filed Jul. 21, 2000, titled “Wave-Division-Multiplexed Transceiver Using Digital Signal Processing,” and to U.S. Provisional Application No. 60,273,215, filed Mar. 1, 2001, titled “High-Speed Analog to Digital Conversion System for Communications Applications,” all of which are incorporated herein by reference in their entireties.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention is directed to receivers and, more particularly, to digital...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H04J3/06H03M1/06H03M1/08H03M1/12H04B10/158H04L25/03
CPCH03M1/0624H03M1/1215H04B10/6933H04B10/697H04B10/6971H04L25/03006H04L25/03057H04L25/03159H03M1/0604H03M1/0607H03M1/0609H03M1/0836H04L7/0054H04L7/0062H04L7/0337H04L25/03133H04L25/03203H04L2025/03445
Inventor AGAZZI, OSCARGOPINATHAN, VENUGOPAL
Owner AVAGO TECH INT SALES PTE LTD
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