56 results about "Adder–subtractor" patented technology

Disclosed is a V-BLAST system for a MIMO communication system. In the V-BLAST system for a MIMO communication system, a pseudo inverse matrix calculator receives a channel transfer function matrix including channel information and produces a cofactor matrix and a determinant for a pseudo inverse matrix. A norm & minimum calculator calculates a minimum index for the cofactor matrix outputted from the pseudo inverse matrix calculator, a weight vector selector selects a row vector having the minimum index and calculates a transposed matrix for the row vector; an adder adds the transposed matrix to a received input symbol, and a subtractor subtracts the determinant to the output. A demapper performs a determined function operation to the output and produces estimated information.

A voltage generating apparatus generates an output voltage based on an input voltage. A voltage generator includes a first operational amplifier operative to receive the input voltage and a feedback voltage proportional to the output voltage. The voltage generator regulates the output voltage so that a virtual short circuit is produced in the first operational amplifier. An output capacitor smoothes the output voltage generated by the voltage generating apparatus. A sense signal generator detects a current flowing in the output capacitor and generates a sense signal proportional to the current detected. An adder-subtractor circuit superimposes the sense signal on at least one of the input and the output of the first operational amplifier.

The invention discloses an iterative polarization code receiver and an iterative polarization code decoding method. The iterative polarization code receiver comprises a detector, a first adder-subtractor, a deinterleaver, an iterative polarization decoder, a second adder-subtractor, a second interleaver and an inverse mapper. According to the iterative polarization code receiver and the iterative polarization code decoding method, the bit error rate and block error rate performances of a wireless communication system can be improved on the condition of not improving the decoding complexity while coding gain is kept, and therefore the user experience is improved.

The invention relates to a two-dimensional discrete cosine transformation (DCT)/inverse DCT circuit and method. The circuit comprises an input memory, a first multiplexer, a register list, a demultiplexer, a DCT /inverse DCT unit, a second multiplexer and an output memory, wherein the input memory, the first multiplexer, the register list, the demultiplexer, the DCT/inverse DCT unit, the second multiplexer and the output memory are sequentially connected, the DCT/inverse DCT unit comprises a register, a first sum-and-difference operation unit and a second sum-and-difference operation unit, the first sum-and-difference operation unit is used for carrying out sum-and-difference operation on the data in the register for once, the second sum-and-difference operation unit is used for carrying out two sum-and-difference operations on the shifted data in the register, the input ends and output ends of the first sum-and-difference operation unit and the second sum-and-difference operation unit are respectively connected with the register, the register is also connected with the demultiplexer and the second multiplexer. The circuit and the method have the advantage that an adder-subtractor and two shifters are used for replacing a multiplier, the particular coefficients are selected, and then the multiplier with more wasted resources and lower speed is not used in the hardware circuit, so a calculation unit of the hardware can be repetitively used.

The invention discloses a dual-voltage-controlled oscillator (VCO) loop-based Sigma-Delta analog to digital converter which belongs to the technical field of analog integrated circuits, in particular relates to a Sigma-Delta analog to digital converter comprising two VCO loops and a three-order filter. The Sigma-Delta analog to digital converter comprises a three-order low-flux filter with two feedforward branches and a feedback branch, two VCO quantizers, an NRZ DAC (Non Return To Zero Digital to Analog Converter) and an RZ DAC, and an adder-subtractor device. According to the VCO loop-based Sigma-Delta analog to digital converter, through the dual VCO loops, the even harmonics of the VCO are eliminated, the nonlinear distortion is reduced, and the adopted three-order low-flux filter comprising the two feedforward branches and the feedback branch, on the premise of ensuring system stability, the nonlinear distortion and the quantizing noise of the VCO quantizers can be further reduced. The Sigma-Delta analog to digital converter can be suitable for being applied at high speed, higher precision and low power consumption when working at a low power supply voltage.

The invention relates to a binary system adder-subtractor, and discloses a binary system adder-subtractor based on an enhancement-type LUT (look up table) 5 structure. According to the invention, the binary system adder-subtractor comprises an enhancement-type 5 input LUT structure, a carry chain structure and a standard xor structure; addition and subtraction logic of two digits is realized for the LUT5 structure by utilizing a LUT 4 with two 3 input share; the port resource utilization ratio achieves 4/5; when controllable addition and subtraction logic (with addition and subtraction control signal input) is realized, the port resource utilization ratio even achieves 5/5=100%; compared with the existing individual 4 input LUT, one digit addition and subtraction is realized, the port utilization ratio is increased by 30%, and the area utilization ratio is improved greatly. Additionally, the carry chain structure comprises two carry look ahead structures; two carry chain logic delays are lowered from two traditional selectors to delay time of a tristate phase inverter; the digit transmission delay is reduced; and the working frequency of the adder-subtractor is improved.

The invention provides a self-adaptive interference cancellation control device which is used in wireless same-frequency relay equipment. The self-adaptive interference cancellation control device comprises an adder/subtractor, an automatic gain control module, an adaptive filter, an interference canceller and a delayer. One input end of the adder/subtracter is connected with a digital down converter in the wireless same-frequency relay equipment; the output end of the adaptive filter is connected with the other input end of the adder/subtracter through the interference canceller; the output end of the adder/subtractor is connected with the input end of the automatic gain control module, one output end of the automatic gain control module is connected with the input end of the self-adaptive filter through the delayer, and the other output end of the automatic gain control module is connected with a digital up-converter in the wireless same-frequency relay device. The invention furtherprovides a self-adaptive interference cancellation wireless same-frequency relay system and a self-adaptive interference cancellation control method, and the self-excitation problem of the wireless same-frequency relay equipment can be effectively solved.

In a method for correcting amplitude and phase offsets in a sigma-delta modulator having a loop including an integrator with a filter and an amplifier, an analog-to-digital converter, a digital-to-analog converter, and an adder-subtractor, an open-loop amplitude/phase frequency response of the modulator is estimated digitally. A phase offset value and an amplitude offset value are calculated by comparing the estimated open-loop amplitude/phase response with a reference amplitude/phase frequency response. The phase and gain offsets of the loop are then compensated for according to the estimated offset values. A sigma-delta modulator implements the method.

A method of acquiring a satellite signal includes calculating a correlation result of a reception signal from a GPS satellite and a replica code using an output value of one adder-subtractor for a combination of addition and subtraction corresponding to time-series change in code values of the replica code from among a plurality of adder-subtractors for addition-subtraction of sampling values obtained by sampling the reception signal in a time series with different combinations of addition and subtraction, and acquiring the satellite signal of the GPS satellite using the correlation result.

A microprocessor (10) comprises a compiler (4), which, for a source program including an integer division q=int(a÷b)(int( ) is a function discarding figures below decimal point in parentheses) for dividing integer a, expressed in N bits, by integer constant b, causes a computer to execute a first process for calculating mb=int(m÷b) (where m=2^N), and a second process for generating an object code, which stores the mb in a first register (24), calculates qx=int(a×mb÷m), calculates rx=a−qx×b, set a quotient q to q=qx when rx<b, or q=qx+1 when rx>=b;

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  • and a microprocessor having an arithmetic circuit (11), which comprises the first register, a multiplier (14), and an adder-subtractor (16), and which executes the object code generated by the compiler.

The invention provides a high precision control system and method for a forging oil press. The high precision control system comprises a press frame and a movable transverse beam moving on the press frame, a mold anvil is installed on the lower surface of the movable transverse beam, a main cylinder is connected to the upper surface of the movable transverse beam through a plunger piston, and a position sensor is arranged on the main cylinder and electrically connected with an adder-subtractor; the adder-subtractor is electrically connected with an input device, the main cylinder is connected with a proportional direction valve through a pipe, and the proportional direction valve, an amplifier, a PID controller and the adder-subtractor are sequentially and electrically connected; and the pipe for connecting the main cylinder with the proportional direction valve is provided with a pressure sensor, and the pressure sensor, a frame deformation convertor and the adder-subtractor are sequentially and electrically connected. By means of the high precision control system and method for the forging oil press, the pressure of the main cylinder is monitored through the pressure sensor, the pressure of the main cylinder is converted into frame deformation Uk, the influences of the frame deformation Uk of the press on Ue are singly considered in the control process, and the control accuracy is higher; and when the pressure changes are larger, the system response speed is higher than that in the prior art.

An integer transforming device for a moving-picture compression encoder, associated with the H.264 standard, comprising: a first adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for input data, generating data extended by a predetermined bit number; a second adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for a shifted result of output data of the first adding/subtracting stage, generating data extended by a predetermined bit number; a third adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for an operation result of the second adding/subtracting stage, generating data extended by a predetermined bit number; and a fourth adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for a shifted result of the third adding/subtracting stage, generating data extended by a predetermined bit number.

Individual A/D converters constituting a time domain A/D converter group according to an embodiment of the present invention each comprises: a reference voltage selection circuit that is connected toa reference signal generation circuit for generating a first reference signal to sweep a full-scale range and a second reference signal to periodically sweep a limited voltage range a plurality of times and that switches between the first and second reference signals that are outputs of the reference signal generation circuit; a comparator that compares the first or second reference signal selected by the reference voltage selection circuit with an input signal; an internal A/D converter that implements an A/D conversion by use of a comparison output signal from the comparator; and a cumulative adder-subtracter that, if the second reference signal has been selected, outputs a signal obtained by averaging A/D conversion values obtained from the A/D conversion.

The invention is a high rigorous number cosine commutation and quantified method without multiplier. Two shifters and one plus-subtracter complete the number cosine commutation with the scale coefficient-s, instead of one multiplier. The commutation export result multiplies with L in order to get DCT commutation result, and s divides quantified coefficient to get the L. The hardware circuit can avoid using the energy-consuming multiplier by selecting given number. It is a kind of no multiplier DCT commutation with massive parallel and consistency. The hardware account unit can be used for many times so the hardware circuit is very simple. The DCT and IDCT can be realized though a hardware circuit and get high account precision.

A variable frequency clock output circuit, comprising: a target value register which stores a target value corresponding to an arbitrarily set target frequency; an increase/decrease value register which stores an arbitrarily set increase/decrease value; an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal; a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide; and a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor.

The invention relates to a method for designing a 16-bit adder-subtractor by utilizing mapping modules, and belongs to the technical field of computer application. The method comprises the following steps of 1: marking a DNA strand by utilizing a domain t and a domain f that represent logic 1 and logic 0 respectively, and establishing a domain-marked DNA signal strand that achieves a medium effect of transferring a signal in a DNA strand displacement reaction, wherein an input/output strand is the DNA signal strand, the DNA signal strand is symmetric in structure, the left half side of the DNA signal strand and a corresponding module of an upstream part can be subjected to the DNA strand displacement reaction, and the right half side of the DNA signal chain and a corresponding module of a downstream part can be subjected to the DNA strand displacement reaction; 2: establishing domain-marked 1 input-mapping modules; and 3: establishing domain-marked 2 input-mapping modules. The logic 1 and the logic 0 are represented through the domain t and the domain f respectively, so that the certainty of the reaction is enhanced and the instability caused by the fact that logic values are represented by concentration is avoided.

An FPGA-based waveform generation circuit and method with adjustable amplitude bias are widely used in the fields of electronic circuits, automatic control, scientific experiments and the like. The circuit is composed of FPGA, DAC, filter circuit and program-controlled amplifier circuit. The method includes determining a waveform data width and a waveform data range. The upper computer generates a cycle of waveform data and corresponding control words according to the set waveform generation parameters. The host computer transmits the waveform data to the FPGA, and the FPGA stores the obtained waveform data in the waveform RAM. FPGA uses DDS and waveform storage RAM to generate waveforms according to the obtained frequency control word and phase control word. The waveform generated by DDS is controlled by the amplitude adjustment module. Set the offset, and adjust the offset by passing the amplitude-adjusted waveform digital quantity through the adder and subtractor. According to the actual test, the loss of waveform amplitude caused by the frequency effect is determined, and the relationship between the waveform amplitude and frequency is determined, so as to control the program-controlled amplification to compensate the waveform amplitude according to this relationship, so as to ensure the accuracy of the amplitude.

The invention discloses a multi-channel comb filter. By decomposition of comb filter transfer function, architecture of the comb filter is optimized. The comb filter is decomposed as a comb filter which is in a multi-phase parallel structure, and by utilization of a shifting register and a random access memory (RAM), a complex comb filter shares an integrator, a comb-shaped device and an adder-subtractor with the multi-channel comb filter. Therefore, on the basis that an area and complexity are not increased, the high-speed multi-channel comb filter is achieved, hardware resource consumption is reduced, cost is saved, working frequency is reduced before the operation of addition and subtraction, and thus the whole working frequency of the comb filter is improved and the multi-channel comb filter is suitable for a next mobile communication system.